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Semiconductor storage device

A storage device and semiconductor technology, applied in semiconductor devices, information storage, read-only memory, etc., can solve problems such as damage to operating characteristics

Pending Publication Date: 2020-09-29
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Among these conductive layers, the conductive layer that functions as the select gate line is further divided and individually selectable, and the operating characteristics may differ depending on the divided conductive layer, resulting in deterioration of the overall operating characteristics.

Method used

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  • Semiconductor storage device
  • Semiconductor storage device
  • Semiconductor storage device

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Experimental program
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no. 1 Embodiment approach

[0020] figure 1 It is a perspective view schematically showing the configuration of the memory cell array 2 included in the semiconductor memory device 1 of the first embodiment. The semiconductor memory device 1 is a NAND (Not AND) type nonvolatile memory including memory cells arranged three-dimensionally.

[0021] In the description below, if figure 1 etc., let the directions perpendicular to each other in a plane parallel to the surface of the semiconductor substrate SUB be the X direction and the Y direction. More specifically, the X direction is the extending direction of the word line WL, and the Y direction is the bit line direction. The extension direction of the line BL. The Z direction is a direction perpendicular to the semiconductor substrate SUB. Therefore, the Z direction is perpendicular to the X direction and the Y direction.

[0022] Such as figure 1 As shown, the semiconductor storage device 1 includes a selection gate SGS, a word line WL, and a selecti...

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Abstract

One embodiment of the present invention provides a semiconductor memory device capable of easily improving operating characteristics. According to one embodiment of the present invention, in the semiconductor memory device, a first semiconductor pillar extends in a first direction in a first region. A second semiconductor pillar extends in the first direction within the second region. A first charge accumulation layer is disposed between the first semiconductor pillar and the first region. A second charge accumulation layer is disposed between the second semiconductor pillar and the second region. A first contact plug is provided at one end side of the third region in the third direction. A third region is a region between the second breaking films in the second conductive layer. A secondcontact plug is provided at one end side of the fourth region in the third direction. A fourth region is a region between the first breaking film and the second breaking film in the second conductivelayer. A third contact plug is provided at the other end side of the third region in the third direction.

Description

[0001] [Related applications] [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2019-50388 (filing date: March 18, 2019). This application includes the entire content of the basic application by referring to this basic application. technical field [0003] This embodiment relates to a semiconductor memory device. Background technique [0004] In a semiconductor memory device having a three-dimensional structure, a plurality of conductive layers are stacked, semiconductor channels penetrate in the stacking direction, and memory cells are arranged at intersections of each conductive layer and the semiconductor channel. In an embodiment in which the conductive layer functioning as the select gate line is further divided and individually selectable among these conductive layers, operating characteristics may differ depending on the divided conductive layer, resulting in loss of overall operating characteristics. Co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11568H01L27/11578
CPCH10B43/30H10B43/20G11C16/08G11C16/0483G11C16/32G11C16/10G11C16/24H10B43/10H10B43/50H10B43/40H10B43/27H10B41/10H10B41/30H10B41/40
Inventor 峯村洋一
Owner KIOXIA CORP
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