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Data packet sorting method and system based on dual-port RAM

A sorting method and data packet technology, which is applied in the field of data transmission, can solve the problems of out-of-order data packets, out-of-order data packets, and different time-consuming data packets.

Active Publication Date: 2020-10-27
ZHENGZHOU XINDA JIEAN INFORMATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] FPGA performs encryption and decryption calculations on data packets. Generally, multiple encryption and decryption operations are used to check the input data packets for parallel processing. However, due to the different lengths of each data packet, each encryption and decryption operation core takes different time to process the corresponding data packets. , which may eventually lead to out-of-order data packets after calculation
At present, there is an urgent need to propose a sorting method to solve the problem of out-of-sequence output data packets caused by parallel operations of multiple encryption and decryption operation cores

Method used

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  • Data packet sorting method and system based on dual-port RAM
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  • Data packet sorting method and system based on dual-port RAM

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Experimental program
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Embodiment 1

[0041] Please also see figure 1 and figure 2 , in a specific application, since the output results of multiple algorithm core operations of the algorithm module may be out of order, the present invention uses a sorting system to sort out the out-of-order data packets, and the sorting system includes an input state machine, a dual Port RAM, register bank, and output state machines. The dual-port RAM is respectively connected to the input state machine and the output state machine for data communication; the dual-port RAM includes n address units 1, 2, 3, ..., n, which are respectively used to receive the corresponding serial number The valid data packet; the register group includes n flag registers 1, 2, 3, ..., n, and the n flag registers are respectively one-to-one corresponding to n address units, and each flag register is used to identify the corresponding address Whether the unit has a valid data packet, if there is a valid data packet, the value of the flag register is...

Embodiment 2

[0055] refer to Figure 4 The difference between this embodiment and Embodiment 1 is that another method for sorting data packets based on dual-port RAM is proposed, and the method includes the following steps:

[0056] Data packet reading phase:

[0057] Step 11, receive data packet a by input state machine kn+i , get the data packet a kn+i Sequence number i, wherein, k=1, 2, ..., m, 1≤i≤n; Let the input state machine have received the last packet of continuous sequence number as packet a p , the input state machine restricts the reception of data packets a within the specified sequence number range q , then p+1≤q≤p+n;

[0058] Step 12, after the input state machine determines the address unit i of the dual-port RAM based on the serial number i, check the value f of the flag register i corresponding to the address unit i i Whether it is equal to 0, if yes, then enter step 13, if no, then wait until the value f of the flag register i i equal to 0;

[0059] Step 13, the ...

Embodiment 3

[0071] The present embodiment provides a packet sorting system based on a dual-port RAM, including an input state machine, a dual-port RAM, a register bank, and an output state machine; the dual-port RAM is connected to the input state machine and the output state machine respectively Data communication connection is performed, and the register group is respectively connected with the input state machine and the output state machine for data communication, so as to realize the data packet sorting method based on dual-port RAM described in embodiment 1 or embodiment 2.

[0072] In the data packet sorting system based on dual-port RAM of this embodiment, the data packet received by the input state machine is a data packet processed by the algorithm module, wherein the algorithm module is connected to the input state machine for data communication , the algorithm module includes a plurality of algorithm cores, and the plurality of algorithm cores can respectively receive data pack...

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Abstract

The invention provides a data packet sorting method and system based on a dual-port RAM. The system comprises an input state machine, a dual-port RAM, a register set and an output state machine. The dual-port RAM is respectively in data communication connection with the input state machine and the output state machine, and the register group is respectively in data communication connection with the input state machine and the output state machine so as to realize the data packet sorting method based on the dual-port RAM. According to the invention, the input state machine is matched with the register set; the out-of-order data packets can be stored in the dual-port RAM in sequence, and then the data packets are read out from the dual-port RAM in sequence through the cooperation of the output state machine and the register block, so that the problem of out-of-order output data packet sequence caused by parallel operation of a plurality of algorithm cores of the algorithm module is effectively solved.

Description

technical field [0001] The invention relates to the field of data transmission, in particular to a data packet sorting method and system based on dual-port RAM. Background technique [0002] FPGA performs encryption and decryption calculations on data packets. Generally, multiple encryption and decryption operations are used to check the input data packets for parallel processing. However, due to the different lengths of each data packet, each encryption and decryption operation core takes different time to process the corresponding data packets. , which may eventually lead to out-of-order phenomena in the data packets after the calculation. At present, there is an urgent need to propose a sorting method to solve the problem of out-of-sequence output data packets after calculations caused by parallel operations of multiple encryption and decryption operation cores. Contents of the invention [0003] In order to solve the above problems, it is necessary to provide a packet...

Claims

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Application Information

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IPC IPC(8): G06F21/60G06F21/72
CPCG06F21/602G06F21/72
Inventor 何骏武元杰余军李鹏展刘武忠乔绍虎
Owner ZHENGZHOU XINDA JIEAN INFORMATION TECH
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