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DRAM interface type detection method and storage medium

A technology of interface type and detection method, applied in the field of storage, can solve the problem of inability to distinguish LPDD2 and LPDD3, affecting the use of software and hardware, etc.

Active Publication Date: 2020-10-30
FUZHOU ROCKCHIP SEMICON
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AI Technical Summary

Problems solved by technology

[0002] The existing technical solutions require separate firmware for different DRAM interface particles. If the type of DRAM interface particles cannot be distinguished, it will affect the cooperation of software and hardware.
Usually by reading MR8 to distinguish particle information but when the chip does not support the use of MR8 reading, then it is impossible to distinguish LPDD2 and LPDD3 at this time

Method used

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  • DRAM interface type detection method and storage medium

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Embodiment Construction

[0012] In order to describe in detail the technical content, structural features, achieved objectives and effects of the technical solution, the following detailed description will be given in conjunction with specific embodiments and accompanying drawings.

[0013] See here figure 1 , A DRAM interface type detection method of this solution, including the following steps: S104 adjusts the DRAM interface read command delay to increase from 8 to 2, and the DRAM interface write command delay to increase by 1 from 4; S106 if there is a certain time After the increase, the DRAM particle access is successful, it is judged as LPDDR3 particle, otherwise it is judged as LPDDR2 particle.

[0014] Among them, the interface read command delay (RL: readlatency) refers to the delay between the issue of the read command and the data echo on the actual data line, and the unit is the number of DRAM interface clock cycles. Interface write command latency (WL: writelatency) refers to the delay from ...

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Abstract

The invention discloses a DRAM interface type detection method and a storage medium, and the method comprises the following steps: adjusting DRAM interface reading instruction delay to be sequentiallyincreased by 2 from 8, and DRAM interface writing instruction delay to be sequentially increased by 1 from 4; and if the DRAM particle access succeeds after a certain increase, judging the DRAM particle as an LPDDR3 particle, otherwise, judging the DRAM particle as an LPDDR2 particle. According to the scheme, the relation between the read instruction delay, the write instruction delay and different DRAM type working responses in practical application is discovered, so that the relation is applied to interface type detection, and the interface type of the DRAM can be effectively identified through the scheme.

Description

Technical field [0001] The present invention relates to the storage field, in particular to a dynamic storage method capable of reducing the occupation of error correction codes. Background technique [0002] The existing technical solutions require separate firmware for different DRAM interface particles. If the type of DRAM interface particles cannot be distinguished, the cooperation of software and hardware will be affected. Usually, the particle information is distinguished by reading MR8, but when the chip does not support MR8 reading, then it is impossible to distinguish LPDD2 from LPDD3 at this time. It is necessary to design a set of DRAM interface type judgment process to solve the above problems. Summary of the invention [0003] For this reason, it is necessary to provide a new method for judging DRAM interface types to solve the problem of distinguishing DRAM interface types; [0004] In order to achieve the above objective, the inventor provides a DRAM interface type ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
CPCG06F3/061G06F3/0659G06F3/0679
Inventor 汤云平
Owner FUZHOU ROCKCHIP SEMICON
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