Cache enabling architecture

Abstract

A cache enabling architecture in which an optical storage reading and / or writing device, a caching processor and a mass writing and reading device are each connected to a data bus. The optical storage reading and / or writing device exchanges information directly with the caching processor over the data bus. The caching uses the mass writing and reading device as cache memory.

Description

technical field [0001] The present invention relates to a cache enabling architecture in which information at the output and / or input of a memory read and / or write device can be cached. The cache-enabling architecture may eg be implemented in a computer system to which said memory reading and / or writing means are connected. In general, the connection takes place via a data bus. Background technique [0002] Caching information from memory devices is a known technique. As examples specifically, many solutions are known to cache random access memory (RAM), hard drives and other mass storage devices. The various storage devices are generally used in computers or in combination with computers. The requirement for caching a storage device is basically to provide a faster memory in which information can be accessed more efficiently than in the storage device, and basically to remove certain information from the storage device The device copies to this faster memory or vice ver...

AI Technical Summary

Problems solved by technology

The solution should utilize existing computer hardware as much as possible

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