Multi-chip debugging method and multi-chip debugging device

Abstract

The invention provides a multi-chip debugging method and a multi-chip debugging device, and belongs to the technical field of communication, and the device particularly comprises a controller which isused for communicating with an external upper computer through a chip connection interface and generating a debugging signal containing a to-be-debugged chip address and a debugging instruction basedon a signal received from the chip connection interface; a cascade control module which is used for receiving the debugging signal output by the controller, adjusting the debugging signal by adoptinga buffer driver, and converting a chip connection interface signal carried by the adjusted debugging signal into a bus slave interface signal capable of accessing a slave interface of the chip to bedebugged; and a bus which is connected with all the chips to be debugged, and is used for acquiring the debugging signal which is output by the cascade control module and is converted into the bus slave interface signal, and transmitting the debugging instruction to the chips to be debugged indicated by the addresses of the chips to be debugged based on the debugging signal. Through the processingscheme disclosed by the invention, the wiring is simple, the maintenance is easy, and the device is suitable for multi-chip debugging.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a multi-chip debugging method and a multi-chip debugging device. Background technique [0002] Chip online debugging is an essential interface for chip design and program development. Generally, the data captured in real time inside the chip is read through the JTAG interface. When multi-chip debugging, multiple JTAG interfaces are required or a debugging interface is used to cascade the chips. However, directly using the JTAG interface for chip debugging, the debugging speed is slow, the amount of data is small, and the number of chip cascades is limited, which is not suitable for a large number of chip cascades; and when using multiple JTAG connectors to debug multi-chips, there are wiring problems. Easy maintenance. Contents of the invention [0003] Therefore, in order to overcome the above-mentioned shortcomings of the prior art, the present invention provides a ...

AI Technical Summary

Problems solved by technology

However, directly using the JTAG interface for chip debugging, the debugging speed is slow, the amount of data is small, and the number of chip cascades is limited, which is not suitable for a large number of chip cascades; and when using multiple JTAG connectors to debug multi-chips, there are complex wiring problems. Easy to maintain

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