A Fully Pipelined Multiply-Add Cell Array Circuit for Convolutional Neural Networks

Abstract

The invention discloses a fully pipelined multiply-add unit array circuit for convolutional neural network, which is characterized in that it includes multiple multiply-add units, and the arrangement of the multiple multiply-add units is as follows: a single multiply-add unit along N units are repeatedly arranged in the first direction, and the n multiplication and addition units are connected together in a cascaded manner to form a multiplication and addition sub-module; the multiplication and addition sub-modules are repeatedly arranged in m along the second direction to form a multiplication and addition core module ; The multiplication and addition core module is repeatedly arranged i along the third direction to form an array circuit including n*m*i multiplication and addition units; wherein m, n and i are integers not less than 2; The first, second and third directions are different. The circuit of the invention can effectively improve the multiplexing rate of data, fully reduce the idle time of the operation unit, and increase the efficiency of convolution operation hardware implementation.

Description

technical field [0001] The invention belongs to the field of artificial intelligence algorithm hardware implementation, and more specifically relates to a fully pipelined multiply-add unit ((Multiplication and Accumulation, MAC)) array circuit for convolutional neural networks. Background technique [0002] In the context of the big data era, the performance of traditional CPUs is no longer sufficient to support large-scale data calculations in artificial intelligence algorithms. The structural design of its general-purpose computing units greatly limits the speed of algorithm prediction and judgment. Due to its high cost and energy consumption, GPU is difficult to be applied on a large scale. Therefore, the design of dedicated hardware circuits for artificial intelligence algorithms that require huge calculations and throughput has broad application prospects. [0003] The convolutional neural network algorithm is one of the most widely used algorithms in artificial intelli...

AI Technical Summary

Problems solved by technology

In addition, the convolutional neural network has a huge amount of calculation and data, and the convolution operation includes a large amount of repeated data multiplication and addition operations. How to design the data flow can improve the data reuse rate in hardware computing as much as possible, making the hardware Computing resources are fully utilized, and the control logic is simple and easy to implement, which is a severe challenge for the hardware design of convolutional neural network algorithms

[0004] Literature "Angel-Eye: A Complete Design Flow for Mapping CNN Onto EmbeddedFPGA", Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Jincheng Yu, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 37, No.1, 2018, A MAC array circuit structure is disclosed, which adopts the strategy of parallel expansion of convolution loops (1), (2) and (4), and realizes high data multiplexing rate through parallel calculation of multiple multiplication units followed by an addition tree structure , but the parallel multiplication mode of this structure causes the calculation unit to be idle during most of the convolution operation, and the control logic is complex, which has the disadvantages of low calculation efficiency and low utilization of hardware resources

In light-weight applications or resource-limited applications, the MAC array circuit structure disclosed in this document is difficult to realize and apply

The data flow and MAC array circuit structure realized by the current research are difficult to achieve high data multiplexing rate, high hardware resource utilization rate and high computing efficiency at the same time

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