Asynchronous test method and system based on multiple virtual PCIE cards

A technology of asynchronous testing and virtual machine, which is applied in the field of testing to achieve wide applicability, reduce the number of tests, and improve the efficiency of testing

Active Publication Date: 2021-02-26
ZHENGZHOU XINDA JIEAN INFORMATION TECH
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problem that the traditional PCIE card testing method cannot realize synchronous performance testing of multiple virtual PCIE devices in the PCIE device, the present invention provides an asynchronous testing method and system based on multiple virtual PCIE cards

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Asynchronous test method and system based on multiple virtual PCIE cards
  • Asynchronous test method and system based on multiple virtual PCIE cards

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] like figure 1 As shown, the embodiment of the present invention provides a kind of asynchronous testing method based on a plurality of virtual PCIE cards, and described method comprises the following steps:

[0054] S101: Plug at least one physical PCIE card into a test host through a physical interface, wherein multiple virtual machines are installed on the test host;

[0055] S102: Virtualize a single physical PCIE card into multiple virtual PCIE cards through SR-IOV technology, and construct a virtual channel for data transmission between each virtual PCIE card and the corresponding virtual machine, each virtual PCIE card includes multiple DMA high-speed channel, multiple BAR low-speed channels and configuration space, the configuration space is used to store virtual PCIE card identification information, the number of DMA high-speed channels, the number of BAR low-speed channels;

[0056] S103: The test application of the test host scans all virtual PCIE cards on ea...

Embodiment 2

[0063] On the basis of the above-mentioned embodiment 1, the difference between the embodiment of the present invention and the above-mentioned embodiment is that this embodiment further optimizes the test process in step S106, and each DMA test thread group includes A DMA sending thread for channel sending test data and a DMA receiving thread for receiving response data, each BAR test thread group includes a BAR sending thread for sending test data to the BAR low-speed channel and a BAR receiving thread for receiving response data, Specifically:

[0064] S1061: The DMA sending thread sends the DMA test data to the corresponding DMA high-speed channel, and the BAR sending thread sends the BAR test data to the corresponding BAR low-speed channel;

[0065] S1062: After the corresponding DMA high-speed channel receives the DMA test data and performs transparent transmission or processing, returns the DMA response data to the corresponding DMA receiving thread; at the same time, t...

Embodiment 3

[0068] In order to test the limit speed of each virtual PCIE card, the embodiment of the present invention also provides a kind of asynchronous testing method based on a plurality of virtual PCIE cards, and the difference from each of the above-mentioned embodiments is that the present embodiment also includes the following steps:

[0069] S108: After the data processing performance of the virtual PCIE card is determined to be qualified, test the limit speed of each DMA high-speed channel through each DMA test thread group corresponding to the test process, and test the speed limit of each BAR low-speed channel through each BAR test thread group limit speed.

[0070] As a kind of implementable mode, the limit speed of each DMA high-speed channel is tested respectively by each DMA test thread group corresponding to the test process, specifically including:

[0071] S1081: The DMA sending thread repeatedly sends DMA test data to the corresponding DMA high-speed channel according...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides an asynchronous test method and system based on multiple virtual PCIE cards. The method comprises the steps of inserting at least one physical PCIE card into a test host througha physical interface, and a plurality of virtual machines are installed on the test host; virtualizing a single physical PCIE card into a plurality of virtual PCIE cards through an SR-IOV technology,and constructing a virtual channel between each virtual PCIE card and the virtual machine; enabling the test application to scan all the virtual PCIE cards on all the virtual machines and start a plurality of test processes; under each test process, starting a virtual PCIE card configuration space monitoring thread; starting a plurality of DMA test thread groups and BAR test thread groups by eachtest process, and asynchronously testing the data processing accuracy of each DMA high-speed channel and each BAR low-speed channel; and for each virtual PCIE card, if a test thread group exceeding apreset threshold feeds back a data processing error of the DMA high-speed channel or the BAR low-speed channel, judging that the data processing performance of the virtual PCIE card is unqualified, and otherwise, judging that the performance is qualified.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to an asynchronous testing method and system based on multiple virtual PCIE cards. Background technique [0002] With the development of modern social science and technology, PCIE bus is widely used in computer systems as a high-performance I / O bus. SR-IOV (Single-Root I / O Virtualization, single root I / O virtualization) is a standard introduced by PCI-SIG, which defines a standard mechanism of PCIE device virtualization technology, which is a part of "virtual channel". A technical implementation for virtualizing a PCIE device into multiple PCIE devices, and each virtual PCIE device provides services to upper-layer software just like a physical PCIE device. [0003] At present, PCIE devices need to be tested for performance after development is completed. Traditional testing methods (such as the PCIe card testing device and method disclosed in patent document CN 110837445 A) can on...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F11/22
CPCG06F11/2221G06F11/2273
Inventor 王斌王中原吴世勇冯驰李银龙卫志刚
Owner ZHENGZHOU XINDA JIEAN INFORMATION TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products