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A Low-Power Register Allocation Compilation Optimization Method

A register allocation and optimization method technology, applied in the computer field, can solve problems such as unsatisfactory energy consumption, achieve the effects of optimizing system operating power consumption, low development cost, and tapping the potential of low power consumption

Active Publication Date: 2022-07-12
JIANGNAN INST OF COMPUTING TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional compilation and optimization technology has been unable to meet the increasing energy consumption. How to reduce the power consumption during operation in an effective and convenient way has become the direction of efforts of those skilled in the art.

Method used

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  • A Low-Power Register Allocation Compilation Optimization Method

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Embodiment

[0022] Embodiment: A low-power register allocation compilation optimization method, based on the following modules:

[0023] The hardware register file enable setting module is used to control the write-back enable bit of the register file: if the enable is turned on, all the specified registers still need to be written back to the register file after bypassing; if the enable is turned off, all the specified registers are bypassed There is no need to write back after the operation, the register still saves the old value, the hardware provides the enable control setting for write back to the specified register file, the default is to write back all registers after bypassing, if you need to specify the register for non-write back operation , open to the software the control setting of the enable bit;

[0024] The software low-power register allocation optimization compiler module is used to analyze the hotspot functions that consume a lot of power in the program and optimize the...

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Abstract

The invention discloses a low power consumption register allocation, compilation and optimization method, comprising the following steps: S1, analyzing the hotspot function and loop segment of the program; S2, counting the execution frequency of the dependency statement in the hotspot code segment; S3, registering the existence of the dependency statement The life cycle of the temporary variable in the middle of the program; S4, turn off the instruction scheduling optimization related to the performance of the dependency statement, to prevent the instruction scheduling due to the consideration of the pipeline performance; S5, perform the basic block on the temporary variable in each dependency statement. Life cycle analysis; S6, perform life cycle analysis across basic blocks for temporary variables in each dependency statement; S7, traverse all basic blocks, and track their definitions and usage points for temporary variables marked for low-power optimization; S8. Perform the optimization of the W_set instruction loop extraction. The invention optimizes the system running power consumption to a certain extent, has low software and hardware development costs, and is simple and direct in reducing power consumption.

Description

technical field [0001] The invention relates to a low-power consumption register allocation, compilation and optimization method, and belongs to the technical field of computers. Background technique [0002] With the continuous development of hardware technology and architecture, the processor speed is getting faster and faster, and the on-chip integration level is getting higher and higher, which not only brings higher processing performance, but also causes huge energy consumption. The development trend of high-performance processors has gradually transitioned from high-performance to high-performance, that is, high-performance energy consumption ratio. Some studies have shown that during the operation of the processor, the power consumption of the register file accounts for 15%~20% of the total power consumption, and a considerable part of the operation value is passed in the pipeline through the bypass, that is, the instruction obtains the source data from the bypass. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/41
CPCG06F8/41G06F8/441G06F8/4432Y02D10/00
Inventor 朱琪吴伟沈莉王飞肖谦周文浩钱宏武文浩
Owner JIANGNAN INST OF COMPUTING TECH
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