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Semiconductor package structure

A packaging structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as cracking, reducing the reliability of semiconductor packaging, and damaging the electrical connection between semiconductor grains and substrates

Pending Publication Date: 2021-03-09
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the semiconductor package may experience warping or cracking, which may damage the electrical connection between the semiconductor die and the substrate, and may reduce the reliability of the semiconductor package.

Method used

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  • Semiconductor package structure
  • Semiconductor package structure
  • Semiconductor package structure

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Embodiment Construction

[0026] The following description is of the best contemplated mode of carrying out the invention. This description is made to illustrate the general principles of the invention and should not be considered in a limiting sense. The scope of the invention is determined by the appended claims.

[0027] The present invention has been described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. In the practice of the invention, the dimensions and relative dimensions do not correspond to actual dimensions.

[0028] figure 1 is a cross-sectional view of a semiconductor package structure 100a according to some embodiments of the present invention. figure 2 yes figure 1 a plan view of the arrangement of holes in t...

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Abstract

The invention discloses a semiconductor package structure, including a substrate having a first surface and an opposite second surface, where the substrate includes a wiring structure; a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure; a second semiconductor die disposed on the first surface and electrically connected to the wiring structure, in which the first semiconductor die and the second semiconductor die are arranged side by side; a molding compound surrounding the first semiconductor die and the second semiconductor die, where the first semiconductor die is separated from the second semiconductor die by the molding compound; and an annular frame mounted on the first surface of the substrate, where the annular frame surrounds the first semiconductor die and the second semiconductor die, where the annular frame includes a constricted region at an outer corner of the annular frame. Thus, warping at corners ofthe substrate is eliminated or reduced when a frame having a wider width is used.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure. Background technique [0002] The semiconductor package can not only protect the semiconductor die from environmental pollutants, but also provide electrical connection between the semiconductor die packaged in the semiconductor package and a substrate (such as a printed circuit board (PCB, printed circuit board)). For example, semiconductor die may be encapsulated in an encapsulating material and electrically connected to the substrate with traces. [0003] However, a problem with such semiconductor packages is that the semiconductor packages are subjected to different temperatures during the packaging process. Due to the different coefficients of thermal expansion (CTE, coefficients of thermal expansion) of various substrates and semiconductor die materials, semiconductor packages may be subjected to high stress. As a result, warpin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L23/31H01L23/488
CPCH01L25/18H01L23/3128H01L24/13H01L24/02H01L2224/02373H01L2224/02381H01L2224/02379H01L2224/13008
Inventor 张嘉诚林子闳彭逸轩林仪柔
Owner MEDIATEK INC
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