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Host and slave device having cascade-connected structure

A device, cascade technology, applied in the direction of computers, digital computer parts, instruments, etc., to achieve the effect of saving costs

Pending Publication Date: 2021-03-09
BEIJING XINNENG ELECTRONIC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the above-mentioned difficulties in the prior art, it is one of the technical problems to be solved in this technology to provide a host and slave devices with a cascaded structure

Method used

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  • Host and slave device having cascade-connected structure
  • Host and slave device having cascade-connected structure
  • Host and slave device having cascade-connected structure

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Embodiment Construction

[0023] The device according to the present invention preferably comprises: a plurality of slaves comprising ports and registers for chip select signal input and output, serial clock input and output and serial data signal input and output respectively and cascaded to each other; and a host, forming and outputting the chip select signal, the serial clock and the serial data signal, wherein the serial data signal includes: an assign byte for controlling the slave; an address byte of a register contained in the slave; and a data byte to be read from or written to the register.

[0024] Hereinafter, the present invention will be described with reference to the accompanying drawings. In describing the present invention, for the sake of brevity and ease of understanding, no distinction is made between individual lines and buses.

[0025] For the same or similar components, symbols such as a, b, and c are added. When description of any one of them is required, symbols can be added ...

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PUM

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Abstract

A device according to the present technology comprises: a plurality of slaves including ports and registers for chip select signal input and output, serial clock input and output, and serial data signal input and output, respectively, and cascaded with each other; the host that forms and outputs a chip selection signal, a serial clock and a serial data signal, and the serial data signal comprisesa setting byte for controlling the slave; address bytes of a register that are contained in slaves; and reading or writing data bytes of the register from or into the register.

Description

technical field [0001] This technology involves a master and slave device with a cascaded structure Background technique [0002] There are various methods of controlling a plurality of slave modules connected to one master. As an example, each slave device may have dedicated input and output ports and perform control signal, data and clock communication between the master and the slave devices in order to control a plurality of slave devices controlled by the master. [0003] When multiple slave devices are to be controlled by a master, as many input and output ports are targeted as there are slave devices controlled by the master. To independently control each slave device and communicate requires a master with massive computing power. Contents of the invention [0004] technical problem [0005] According to the prior art, there are as many input and output ports as targets as the number of slave devices controlled by the master, which is not economical because a lar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/173
CPCG06F15/173G06F13/42G06F13/4282G06F13/4068G09G3/20
Inventor 金镇赫金钟善
Owner BEIJING XINNENG ELECTRONIC TECH CO LTD