Wafer testing method, device and equipment and storage medium
A technology of wafer testing and testing methods, which is applied in semiconductor/solid-state device testing/measurement, electrical components, semiconductor/solid-state device manufacturing, etc. effect of time
Active Publication Date: 2021-04-16
HUA HONG SEMICON WUXI LTD
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[0004] The present application provides a wafer testing method, device, equipment and storage medium, which can solve the problem that the wafer testing method provided in the related art takes a long time
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[0029] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.
[0030] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...
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The invention discloses a wafer test method, device and equipment and a storage medium. The method comprises the steps of obtaining test key coordinates of a target wafer; obtaining an abnormal coordinate of the target wafer, wherein the abnormal coordinate is a coordinate counted according to a test result of a wafer which is the same as the target wafer; determining a target measurement area on a coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, wherein the target measurement area comprises the test key coordinates and coordinates overlapped in the abnormal coordinates and the coordinate map; and carrying out wafer testing on the target measurement area. According to the invention, the target measurement area is determined on the coordinate map of the target wafer according to the test key coordinates and the abnormal coordinates, the probe of the wafer test equipment is controlled, the wafer test is carried out on the target measurement area on the target wafer on the slide holder of the wafer test equipment, and since all areas on the target wafer do not need to be measured, the wafer measurement time is shortened, and the manufacturing efficiency of an integrated circuit is improved.
Description
technical field [0001] The present application relates to the technical field of integrated circuit manufacturing, in particular to a wafer testing method, device, equipment and storage medium. Background technique [0002] Wafer test (wafer test), such as wafer acceptance test (wafer accept test, WAT), is the electrical measurement of semiconductor devices on the wafer after the integrated circuit process is completed, and is used to check whether the process of each stage is Compliant with the standard, the test items include device characteristic test, capacitance test, contact resistance test and breakdown test, etc. [0003] In the related art, the method for testing the wafer is to place the wafer on a carrier table and contact the wafer with a probe to detect each chip (die) on the wafer. However, due to the large number of chips on the wafer (especially a wafer larger than 8 inches), it takes a long time to inspect each chip on the wafer, resulting in low manufactur...
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IPC IPC(8): H01L21/66H01L21/67
Inventor 王善屹
Owner HUA HONG SEMICON WUXI LTD