A clock phase selection circuit

Abstract

The invention provides a clock phase selection circuit, which includes M data acquisition modules, a decoder and a clock selection module. The M data collection modules respectively collect the instantaneous values ​​of the candidate clocks whose phases are sequentially delayed by the M channels at the rising edge of the communication field clock and transmit them to the decoder. When the data at the i-th input terminal is 0 and the data at the i-1-th input terminal is 1, the decoder sets the data at the i-1-th output terminal to 1, and sets the data at the other output terminals to 0. The clock selection module outputs one candidate clock corresponding to the output terminal whose data is set to 1 among the M output terminals of the decoder as the output clock. The clock phase selection circuit provided by the present invention only needs a few cycles of the communication field clock to select a candidate clock with a similar phase. Compared with the method of only using a digital phase-locked loop circuit, it improves the phase change locking of the communication field clock. Response time of candidate clock outputs that are close in phase.

Description

technical field [0001] The present invention relates to the technical field of NFC (Near Field Communication, near field communication), and more specifically, relates to a clock phase selection circuit. Background technique [0002] In the NFC scheme, the reader generates a communication field with a frequency of 13.56MHz. The NFC card communicates with the card reader by reading the strength of the communication field sent by the card reader, and the speed of data transmission is also synchronized with the frequency of the communication field. This requires the clock in the NFC card to be consistent with the clock in the communication field sent by the card reader in terms of frequency and phase. [0003] The commonly used method at present is to use a digital phase-locked loop to realize that the required clock is consistent with the clock frequency of the communication field. However, the phase adjustment of the digital phase-locked loop is a very slow process. If the ...

AI Technical Summary

Problems solved by technology

However, the phase adjustment of the digital phase-locked loop is a very slow process. If the phase of the communication field clock changes, the digital phase-locked loop cannot lock to the same phase as the communication field clock in a short time

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