Calibration method and device

Abstract

The invention discloses a calibration method, a device and a corresponding delay circuit. The method is used for carrying out the time sequence calibration of a controller connected to a memory, and comprises the steps: carrying out the period calibration of a clock signal of the controller based on a preset period calibration parameter, enabling a sampling point for sampling read data of the memory by the controller to be positioned in a data segment of the read data; and performing coarse calibration on a clock signal of the controller based on a preset coarse calibration parameter, so that the sampling point is located in a single data width in the data segment. According to the invention, the controller can quickly and accurately determine the sampling point of the read data of the memory.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a calibration method and device. Background technique [0002] When the memory is connected to the controller, in order to ensure that the controller can access the memory normally, the clock signal of the controller needs to be calibrated, otherwise the memory cannot receive the correct data sent by the controller, and the controller cannot The correct data was read from the memory. see figure 1 , the time calibration of the memory output read data (DQ signal) is determined by the parameters tWCK2CK and tWCK2DQO, tWCK2CK and tWCK2DQO are two parameters defined in the GDDR6 specification, where tWCK2CK represents the clock signal WCK of the controller and the clock signal CK of the memory Deviation, tWCK2DQO represents the delay from the clock signal WCK of the controller to the DQ output, this time is a nanosecond delay, and it is time-consuming to calibrate the delay of this m...

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Problems solved by technology

see figure 1 , the time calibration of the memory output read data (DQ signal) is determined by the parameters tWCK2CK and tWCK2DQO, tWCK2CK and tWCK2DQO are two parameters defined in the GDDR6 specification, where tWCK2CK represents the clock signal WCK of the controller and the clock signal CK of the memory Deviation, tWCK2DQO represents the delay from the clock signal WCK of the controller to the DQ output. This time is a nanosecond delay. It is time-consuming to calibrate the delay of this magnitude.

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