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Circulating current suppression method applied to three-level inverter

A circulating current suppression and inverter technology, which is applied in the direction of irreversible DC power input to AC power output, AC power input to DC power output, and output power conversion devices, etc., can solve problems such as low delay

Active Publication Date: 2021-06-01
DELTA ELECTRONICS INC
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

In order to make the instantaneous common-mode voltage of each three-level inverter equal and avoid the generation of circulating current, when multiple three-level inverters are connected in parallel, the current practice is to use each three-level inverter to generate a pulse width modulation signal Carrier synchronization is carried out so that each three-level inverter maintains the same instantaneous switching state, so that the instantaneous common-mode voltages of multiple three-level inverters connected in parallel are equal. However, this method requires multiple three-level inverters. There is a high-frequency, low-latency mutual communication method between the inverters of the hierarchy, so that each three-tier inverter will incur additional communication costs

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  • Circulating current suppression method applied to three-level inverter
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Embodiment Construction

[0029] Some typical embodiments embodying the features and advantages of the present disclosure will be described in detail in the description in the following paragraphs. It should be understood that the present disclosure can have various changes in different embodiments without departing from the scope of the present disclosure, and the descriptions and illustrations therein are used for illustration in nature rather than limiting the present disclosure .

[0030] see Figure 5 , Figure 6 and Figure 7 ,in Figure 5 It is a flow chart of the steps of the circulation suppression method of the preferred embodiment of the present disclosure, Figure 6 for Figure 5 The circuit structure diagram of the three-level inverter applied by the circulating current suppression method shown, Figure 7 for three-level inverter applications Figure 5 In the circulating current suppression method shown, the timing diagram of the first implementation of the three-phase command volta...

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Abstract

The invention provides a circulating current suppression method applied to a three-level inverter, which comprises the following steps of translating a switching state corresponding to a phase command voltage belonging to an intermediate voltage in three-phase command voltages, so that the switching state corresponding to the intermediate voltage and the switching state corresponding to the phase command voltage with the same polarity are not overlapped and are connected with each other. Therefore, under the condition that the three-phase command voltage is balanced and the zero-sequence voltage is not added, the sum of the three-phase instantaneous output voltage output by the three-stage inverter is zero, that is, the common-mode voltage generated by the three-stage inverter is zero.

Description

technical field [0001] The disclosure belongs to the field of three-level inverters, and in particular relates to a method for suppressing circulating current applied to three-level inverters. Background technique [0002] Three-level inverters, such as neutral point clamped (NPC) inverters, are often used for high-power applications, such as converting three-phase AC power to drive loads. Compared with the two-level inverter, the cross voltage of the switching element of the neutral point clamped inverter is only half of that of the two-level converter under the same DC link voltage. In addition, the neutral point clamped inverter can output three levels of phase output voltage and five levels of line-to-line output voltage, so it can effectively reduce the harmonic components of the output voltage and current. In the three-level inverter, it is common to use space vector pulse width modulation, such as phase configuration pulse width modulation (Phase disposition pulse wi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02M7/48H02M7/487H02M7/493H02M7/5387H02M1/12
CPCH02M7/48H02M7/487H02M7/493H02M7/53871H02M1/126
Inventor 蔡孟江郑博泰胡凯维邢雷锺王荟雅
Owner DELTA ELECTRONICS INC