Method, system and equipment for improving reading speed of flash memory and storage medium

A technology of reading speed and flash memory, which is applied in a method of improving the reading speed of flash memory, equipment and storage media, and the system field. It can solve the problems of slow reading speed of NAND Flash and affect the performance of NAND controller, etc., so as to reduce the number of re-reading , the effect of improving the reading speed

Active Publication Date: 2021-06-18
SHENZHEN SANDIYIXIN ELECTRONICS CO LTD
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Problems solved by technology

At this time, it is necessary to re-read (Read Retry) the ECC block, that is, change the offset of the current read voltage through parameter adjustment, re-read the data and cooperate with ECC for error correction. If the parameter adjustment method is unreasonable, it will cause multiple reads and errors. Checking, thus affecting the performance of the NAND controller due to too many read times, resulting in a very slow read speed of NAND Flash

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  • Method, system and equipment for improving reading speed of flash memory and storage medium
  • Method, system and equipment for improving reading speed of flash memory and storage medium
  • Method, system and equipment for improving reading speed of flash memory and storage medium

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[0040] In order to make the purpose, technical solutions and advantages of this application clearer, the following in conjunction with the attached Figure 1-5 And embodiment, this application is described in further detail. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application.

[0041] In NAND Flash flash memory, the floating gate field effect transistor (Floating Gate FET) is used as the basic storage unit to store data. The floating gate field effect transistor has four terminal electrodes, which are source (Source), drain (Drain), control Gate (Control Gate) and Floating Gate (Floating Gate), the main difference between Flash and ordinary MOS tubes is the floating gate. Flash injects and releases charges through the floating gate to represent '0' and '1'. When charges are injected into the floating gate, there is a conductive channel between D and S, and '0' is read fro...

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Abstract

The invention relates to the field of storage devices, in particular to a method, a system and equipment for improving the reading speed of a flash memory and a storage medium, and the method comprises the following steps: outputting a rereading instruction in response to a starting instruction; responding to the re-reading instruction, and sequentially calling different voltage threshold gear groups in a voltage threshold gear table to perform re-reading operation; and when the rereading operation is successful, adjusting the corresponding voltage threshold gear group to the front order, and forming a new voltage threshold gear table to be used for the next rereading operation. The sequence of the voltage threshold gear sets in the voltage threshold gear table is dynamically adjusted, it is always guaranteed that the most effective voltage threshold gear sets are ranked in the front, it is guaranteed that the most effective voltage threshold gear sets are used preferentially, and therefore the re-reading frequency is reduced, and the reading speed of the flash memory is increased.

Description

technical field [0001] The present application relates to the field of storage devices, in particular to a method, system, device and storage medium for increasing the reading speed of flash memory. Background technique [0002] NAND Flash is a kind of Flash memory, which is a non-volatile storage device. Due to the characteristics of NAND Flash, each page of Flash data is divided into one or more ECC blocks. When data is written, each ECC block must be ECC error correction coding; when reading data, each ECC block performs ECC error correction decoding to ensure that the data of this ECC block is correct. The full name of ECC is Error Checking and Correction, which is an error detection and correction algorithm for NAND. In NAND memory cells, some are inherently broken or unstable, and as NAND continues to be used, there will be more and more bad memory cells. Therefore, the data written by the user to NAND must be protected by ECC, so that even if some of the bits are re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/12G11C16/26
CPCG11C16/12G11C16/26Y02D10/00
Inventor 李俊杰胡来胜张辉张如宏陈向兵
Owner SHENZHEN SANDIYIXIN ELECTRONICS CO LTD
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