Supercharge Your Innovation With Domain-Expert AI Agents!

Chip FT and EQC integrated test method and system

A test method and a test system technology, which are applied in the direction of faulty hardware test method, error detection/correction, and detection of faulty computer hardware, etc., can solve problems such as test inconvenience, increase manpower and material costs, and low test efficiency. The effect of test efficiency, saving time cost and labor cost, and convenient test operation

Inactive Publication Date: 2021-06-29
珠海芯业测控有限公司
View PDF4 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, in the industry's chip testing process that integrates testing and editing, after the FT test is completed, it is often necessary to disassemble the tape and then extract a part for EQC testing. This method of testing is very inconvenient, wastes time, and has low test efficiency. It also increases manpower. and material cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip FT and EQC integrated test method and system
  • Chip FT and EQC integrated test method and system
  • Chip FT and EQC integrated test method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0027] In the description of the present invention, the meaning of several means one or more, and the meaning of multiple means two or more than two. Greater than, less than, exceeding, etc. are understood as not including the original number, and above, below, within, etc. are understood as including the original number . If the description of the first and second is only for the purpose of distinguishing the technical features, it cannot be understood as indicating or implying the relative importance or implicitly indicating the number...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a chip FT and EQC integrated test method and system, and the method comprises the following steps: an upper computer operates a corresponding test program according to a test request, reads burning code data from the test program based on a test configuration table, and transmits the burning code data to a single-chip microcomputer in an interruption manner; the single-chip microcomputer receives the code burning data, stores the code burning data in the RAM, and burns the code burning data into the chip to be tested; and the host computer performs FT test on the chips to be tested through the single-chip microcomputer, and if the number of the chips to be tested passing the FT test is detected to be greater than or equal to a preset EQC test demand number, the EQC test is performed on the chips to be tested passing the FT test. According to the invention, online burning integration of the to-be-tested chip is realized, the test efficiency is improved, the time cost and the labor cost are saved, only the test program of the upper computer needs to be modified for different burning codes of the same chip, the single-chip microcomputer does not need to be modified again, and the test operation is more convenient.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a chip FT and EQC integrated testing method and system. Background technique [0002] After the chip is packaged, it will be tested by FT (Final Test), also known as Package Test (Package Test), and EQC (Electronic Quality Control) test. The FT test is to test the function of each IC and its specified standards after packaging. EQC is to check the internal coding of the chips that pass the test, and check whether there are any wrong coding products in this batch of chips. When the EQC test fails, the batch of chips will be re-tested. [0003] At present, in the industry's chip testing process that integrates testing and editing, after the FT test is completed, it is often necessary to disassemble the tape and then extract a part for EQC testing. This method of testing is very inconvenient, wastes time, and has low test efficiency. It also increases manpower. and material c...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F11/22G06F8/61G06F9/445
CPCG06F11/2205G06F11/2273G06F8/63G06F9/4451
Inventor 吴春诚徐磊赵世伟
Owner 珠海芯业测控有限公司
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More