Faster access of virtual machine memory backed by host computing device's virtual memory

A memory and computer technology, applied in memory systems, memory architecture access/allocation, computing, etc., can solve problems that prevent users from obtaining security benefits, low efficiency, etc.

Pending Publication Date: 2021-07-23
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such inefficiencies may prevent users from reaping the security benefits and other benefits of accessing storage through a hypervisor

Method used

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  • Faster access of virtual machine memory backed by host computing device's virtual memory
  • Faster access of virtual machine memory backed by host computing device's virtual memory
  • Faster access of virtual machine memory backed by host computing device's virtual memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0018] The following description relates to improving the efficiency of memory access while providing more efficient memory utilization on a computing device hosting one or more virtual machine processes providing a virtual machine computing environment. To improve memory utilization efficiency of virtual machine processes executing on a host computing device, these virtual machine processes may be backed by the host's virtual memory such that conventional virtual memory efficiencies may be applied to the memory consumed by such virtual machine processes. In the case where the guest physical memory of a virtual machine environment is backed by virtual memory allocated to one or more processes executing on the host computing device, in order to increase the level of traversal of a Layer 2 Address Table (SLAT) as part of a memory access One or more levels of tables within the SLAT may be skipped or otherwise not referenced at a speed of 100, resulting in more efficient SLAT trave...

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PUM

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Abstract

To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Description

Background technique [0001] Modern computing devices operate by executing computer-executable instructions in high-speed volatile memory in the form of random access memory (RAM), and execution of such computer-executable instructions typically requires reading data from RAM. Due to cost, physical size limitations, power requirements, and other similar constraints, computing devices typically include less RAM than is typically required by processes executing on such computing devices. To accommodate such constraints, virtual memory is utilized whereby it appears that the memory available to processes executing on the computing device is larger than that provided by the physical memory circuitry. The relationship between virtual memory and physical memory is typically managed by one or more memory managers, which implement, maintain, and / or refer to "page tables" whose information describes one or more virtual memory addresses The relationship to the location of corresponding ...

Claims

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Application Information

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IPC IPC(8): G06F12/1036G06F12/1009G06F12/109G06F12/08G06F9/50G06F12/02G06F12/126
CPCG06F2212/151G06F2212/651G06F2212/1024G06F2212/1052G06F2212/683G06F12/1036G06F2212/657G06F12/1009G06F12/109G06F2212/654G06F2212/652G06F2212/656G06F12/08G06F12/126G06F9/5077G06F12/023G06F9/45558G06F12/1063G06F2009/45583G06F2212/50G06F12/0882G06F12/0811
Inventor Y·巴克M·埃伊根A·U·基山
Owner MICROSOFT TECH LICENSING LLC
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