Efficient interleaver and interleaving method for LDPC (Low Density Parity Check) decoder

Abstract

The invention discloses a high-efficiency interleaver and an interleaving method for an LDPC decoder, the interleaver uses a distributed RAM in an FPGA as a main implementation resource, and through the design of read-write address control and a storage structure, the functions of p node sequence-changing reading, processing and original sequence write-back which need to be completed by adopting a Benes network in a traditional structure are completed; while the working requirement of the LDPC decoder of the TDMP is met, the resource and throughput rate requirements are considered. Compared with the traditional interleaver, the interleaver disclosed by the invention has the advantages that the resource consumption is greatly reduced on the premise of ensuring the read-write efficiency, and the resource utilization rate of the FPGA is improved.

Description

technical field [0001] The invention belongs to the technical field of channel coding, in particular to an efficient interleaver and an interleaving method for an LDPC decoder. Background technique [0002] The LDPC code is a good code close to the Shannon limit, and its decoding methods mainly include the conventional TPMP (Tow Phase Message Passing) method and the TDMP (Turbo Decoding Message Passing) method. In general, TDMP decoding converges faster, that is, better performance can be obtained under the same number of iterations, or faster convergence can be achieved under the same performance, thereby reducing the decoding time. Some specially constructed quasi-cyclic LDPC codes (Quasi-Cyclic LDPC) are very suitable for TDMP decoding. Compared with the traditional TPMP method, TDMP can effectively improve the throughput of the decoder under the premise of ensuring the decoding performance. , Reducing decoding delay, is an effective low-delay decoding method. The decod...

AI Technical Summary

Problems solved by technology

The disadvantage is that when the code length becomes longer, the resource consumption increases exponentially

According to the actual implementation results on the FPGA platform, implementing an 8×8 Benes network, that is, an 8-node interleaver requires 896 logic units, while a 64×64 Benes network requires 11,264 logic units. When the scale of the Benes network is large, the required resources are very considerable, that is to say, it is difficult to realize the large-scale Benes network in FPGA.

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