Reconfigurable computing structure, computing method and hardware architecture

Abstract

The present invention provides a reconfigurable computing structure, computing method and hardware architecture. The computing structure includes: a first semiconductor structure and a second semiconductor structure; the first semiconductor structure is connected to the second semiconductor structure, and the first semiconductor structure includes a memory and a logic circuit, the second semiconductor structure includes a reconfigurable array, and the reconfigurable array includes a plurality of reconfigurable operators; the logic circuit is used to obtain the operation algorithm to be executed from the memory, and based on the operation algorithm, reconfigurable The reconfigurable operators in the array are configured to determine the operation array corresponding to the operation algorithm, so that the second semiconductor structure executes the operation algorithm based on the operation array. The present invention flexibly configures the corresponding reconfigurable operators according to the calculation algorithms in different scenarios, and at the same time reduces the data transfer distance between the memory and the logic circuit, thereby reducing power consumption and delay, and breaking through the limitation of planar technology , increasing the storage space of computing logic resources.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a reconfigurable computing structure, computing method and hardware architecture. Background technique [0002] At present, many application requirements include multiple complex operations. For example, a multimedia application may include subtasks such as data parallel processing, bit processing, irregular computing, high-precision word operations, and operations with real-time requirements. The processing system is required to be flexible. Handle the above-mentioned subtasks efficiently. [0003] However, the traditional computing structure uses fixed hardware resources for computing, and cannot flexibly configure corresponding hardware resources according to different computing tasks. In addition, in the traditional solution, the memory and the logic circuit are separated on two chips, resulting in a long data transfer path from the memory to the logic circuit, whi...

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a reconfigurable computing structure, computing method, and hardware architecture to solve the problem of inability to flexibly configure hardware resources according to different computing tasks in the prior art, and the data transfer distance from the memory to the logic circuit is long, which increases power consumption and delay defects

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