Reconfigurable computing structure, computing method and hardware architecture

Abstract

The invention provides a reconfigurable computing structure, a computing method and a hardware architecture. The computing structure comprises a first semiconductor structure and a second semiconductor structure; the first semiconductor structure is connected with the second semiconductor structure, the first semiconductor structure comprises a memory and a logic circuit, the second semiconductor structure comprises a reconfigurable array, and the reconfigurable array comprises a plurality of reconfigurable operators; and the logic circuit is used for acquiring the operation algorithm to be operated from the memory, configuring the reconfigurable operators in the reconfigurable array based on the operation algorithm, and determining an operation array corresponding to the operation algorithm, so that the second semiconductor structure executes the operation algorithm based on the operation array. According to operation algorithms in different scenes, corresponding reconfigurable operators are flexibly configured, meanwhile, the data carrying distance between a memory and a logic circuit is reduced, power consumption and time delay are further reduced, the limitation of a plane process is broken through, and the storage space of computational logic resources is increased.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a reconfigurable computing structure, computing method and hardware architecture. Background technique [0002] At present, many application requirements include multiple complex operations. For example, a multimedia application may include subtasks such as data parallel processing, bit processing, irregular computing, high-precision word operations, and operations with real-time requirements. The processing system is required to be flexible. Handle the above-mentioned subtasks efficiently. [0003] However, the traditional computing structure uses fixed hardware resources for computing, and cannot flexibly configure corresponding hardware resources according to different computing tasks. In addition, in the traditional solution, the memory and the logic circuit are separated on two chips, resulting in a long data transfer path from the memory to the logic circuit, whi...

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Problems solved by technology

[0004] The present invention provides a reconfigurable computing structure, computing method, and hardware architecture to solve the problem of inability to flexibly configure hardware resources according to different computing tasks in the prior art, and the data transfer distance from the memory to the logic circuit is long, which increases power consumption and delay defects

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