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Cavity detection method for 3D NAND memory

A technology for void detection and memory, which is applied in semiconductor/solid-state device testing/measurement, electric solid-state devices, semiconductor devices, etc., can solve problems such as leakage, affecting the yield rate of 3D NAND memory products and production efficiency, etc., to prevent abnormal leakage and improve The effect of production efficiency and product yield

Active Publication Date: 2021-09-17
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology

[0004] Wherein, during the process of forming the filling layer, a void may be formed in the filling layer, and after removing the sacrificial layer and filling the conductive material to form the gate, the void will make the bottom selective gate (BSG) communicate with the substrate, And cause abnormalities such as leakage, which in turn affects the product yield and production efficiency of 3D NAND memory

Method used

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  • Cavity detection method for 3D NAND memory
  • Cavity detection method for 3D NAND memory
  • Cavity detection method for 3D NAND memory

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Embodiment Construction

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0015] In the description of the present application, the terms "first", "second", etc. are used to distinguish different objects, not to describe a specific order or indicate the number of indicated technical features. In addition, the terms "upper", "inner ", "Outside", "Top", "Bottom", "Thickness" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describi...

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Abstract

The invention provides a cavity detection method for a 3D NAND memory. The cavity detection method comprises the following steps: removing a part, located on a plurality of stacked structures arranged at intervals, of a filling layer; removing the second sacrificial layers and the parts, between the adjacent second sacrificial layers, of the filling layer; removing the second insulating layers and the parts, located between the adjacent second insulating layers, of the filling layer; forming a protection layer covering the side wall and the bottom of the substrate; and processing the 3D NAND memory by using a first wet etching process and carrying out cavity detection. According to the void detection method provided by the invention, the filling layer is partially removed to expose the top surface of the part, between the adjacent first sacrificial layers, of the filling layer, and then the substrate is processed by using the first wet etching process. Whether the filling layer has a hole is determined by detecting whether the substrate has an etching trace, so that the 3D NAND memory is prevented from generating electric leakage abnormity.

Description

technical field [0001] The present application relates to the technical field of memory manufacturing, in particular to a method for detecting voids in 3D NAND memory. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] At present, the manufacturing process of 3D NAND memory includes: forming a stack layer composed of insulating layers and sacrificial layers alternately stacked on the substrate; trimming and etching the stack layer to form a stack of multiple intervals in a stepped shape structure; forming a filling layer, and the filling layer fills the space a...

Claims

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Application Information

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IPC IPC(8): H01L21/66H01L27/11556H01L27/11582
CPCH01L22/12H10B41/27H10B43/27Y02D10/00
Inventor 韩烽陈金星马霏霏
Owner YANGTZE MEMORY TECH CO LTD
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