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An error rate analysis method, system and device for an MLC chip

An analysis method and error rate technology, applied in the field of error rate analysis, can solve the problems of MLC chip data block error rate analysis, comprehensive analysis of unfavorable MLC chip performance, etc.

Active Publication Date: 2021-11-09
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the single-bit global analysis method cannot analyze the error rate of the specific data block (block) and page (page) of the MLC chip, which is not conducive to a comprehensive analysis of the performance of the MLC chip

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  • An error rate analysis method, system and device for an MLC chip
  • An error rate analysis method, system and device for an MLC chip
  • An error rate analysis method, system and device for an MLC chip

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Embodiment Construction

[0046] The core of the present invention is to provide an error rate analysis method, system and device of an MLC chip, which can analyze the error rate of specific data blocks and pages of the MLC chip, and can analyze the errors of specific data blocks and pages in different bit states The rate is conducive to the comprehensive analysis of the performance of the MLC chip.

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection...

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Abstract

The invention discloses an error rate analysis method, system and device of an MLC chip. A data block is selected from an MLC chip, and the data block is erased and written; Each group of dibits corresponding to the first page and the second page, and determine the bit status of each group of dibits; count the first total number of all dibits corresponding to the target page in the target bit status indicating data write errors , so as to obtain the first error rate of the target page in the target bit state; count the second total number of all dibits corresponding to the data block in the target bit state, so as to obtain the second error rate of the data block in the target bit state Error rate to analyze chip performance based on first / second error rate. It can be seen that the present application can analyze the error rate of the specific data block and page of the MLC chip, and can analyze the error rate of the specific data block and page under different bit states, which is beneficial to the comprehensive analysis of the performance of the MLC chip.

Description

technical field [0001] The invention relates to the storage field, in particular to an error rate analysis method, system and device of an MLC chip. Background technique [0002] At present, NAND Flash (non-volatile flash memory) is widely used and suitable for various storage occasions. In terms of its architecture, it is divided into SLC (Single-Level Cell, single-level storage unit, which refers to a storage unit that can Store 1 bit of data, there are two cases of 0 and 1), MLC (Multi-Level Cell, double-layer storage unit, refers to a storage unit that can store 2 bits of data, there are (11, 10, 01 , 00) in four cases) and TLC (Triple-Level Cell, three-layer storage unit, which means that a storage unit can store 3 bits of data, there are (000, 001, 010, 011, 100, 101, 110 , 111) 8 cases) three. Among them, the MLC chip is the current mainstream memory chip, and the performance of the MLC chip mainly depends on the error rate of the data written in the MLC chip (it is...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F15/78G11C16/16G11C29/44
CPCG06F3/0619G06F3/064G06F3/0653G06F15/7807G11C16/16G11C29/44G11C29/52G06F11/3037G06F11/3034G06F2201/88G06F11/3409G06F11/076
Inventor 王敏张闯任智新
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD