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Enhanced Auxiliary Interface Systems and Methods

An auxiliary interface and test system technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems such as not allowing the use of more than 10 or 12 devices in parallel, and limited input and output I/O space.

Pending Publication Date: 2021-10-01
ADVANTEST CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional test systems and methods often have various limitations
[0005] Conventional CPU platforms (for example, Intel x86 architecture platforms, etc.) usually have limitations on input and output I / O space
I / O space limitations in turn limit the number of devices that can be tested in parallel on the same interface
For example, a UART device sitting behind a PCIe switch usually does not allow more than 10 or 12 devices to be used in parallel

Method used

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  • Enhanced Auxiliary Interface Systems and Methods
  • Enhanced Auxiliary Interface Systems and Methods
  • Enhanced Auxiliary Interface Systems and Methods

Examples

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Embodiment Construction

[0018] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure...

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Abstract

The present invention provides an enhanced auxiliary interface systems and methods. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel.

Description

[0001] related application [0002] This application claims benefit and priority, which application is incorporated herein by reference. technical field [0003] The invention relates to the field of electronic testing. Background technique [0004] Electronic systems and devices have contributed significantly to the advancement of modern society and have facilitated increased productivity and reduced costs in analyzing and communicating information in a variety of business, scientific, educational, and entertainment applications. Conventional testing systems and methods often have various limitations. [0005] Conventional CPU platforms (for example, Intel x86 architecture platforms, etc.) usually have limitations on input and output I / O space. I / O space limitations in turn limit the number of devices that can be tested in parallel on the same interface. For example, a UART device sitting behind a PCIe switch usually does not allow more than 10 or 12 devices to be used...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G01R31/00
CPCG06F13/4068G01R31/00G06F13/4282G06F13/1668G06F11/2733G01R31/31715G01R31/31713G01R31/3181G06F2213/0026
Inventor 元驰斯德詹·马利西奇
Owner ADVANTEST CORP