Chip failure analysis method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a physical failure analysis method and device of a chip, electronic equipment and a storage medium, relates to the technical field of semiconductor processing, and can effectively improve the failure analysis efficiency of the chip. The method comprises the following steps: according to electrical failure analysis, acquiring position information of a suspicious failure point in a target chip, wherein he position information comprises a layout corresponding to a target layer where the suspicious failure point is located in the target chip and the position of the suspicious failure point in the target layer; according to the position information of the suspicious failure point, obtaining a chip image in a preset range in the target chip and a first image, wherein the preset range corresponds to the position information; performing contour recognition on the first image through a preset image recognition model to obtain a second image; and determining a physical failure condition of the suspicious failure point according to the second image and a layout corresponding to the target layer. The method is suitable for chip failure analysis.

Description

technical field [0001] The invention relates to the technical field of semiconductor processing, in particular to a chip failure analysis method and device, electronic equipment, and a storage medium. Background technique [0002] When a process abnormality causes a chip failure, eFA (electrical failure analysis, electrical failure analysis) is often used first to find potential failures. For example, the current SCAN (scanning) diagnosis is a wide and effective electrical failure analysis method, and the potential failure point location and corresponding circuit layout can be obtained through the analysis of this method. After the eFA analysis obtains the location of the failure point, it is necessary to manually find the corresponding failure point in the chip, and perform a physical failure analysis (PFA) on the failure point in order to improve the process. [0003] However, due to the continuous reduction of integrated circuit size and the continuous increase of circui...

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Problems solved by technology

[0003]However, due to the continuous reduction of integrated circuit size and the continuous increase of circuit density, according to the location of the suspected failure point and the circuit layout provided by eFA, the corresponding The point of failure also takes a lot of time and is inefficient

Especially as the manufacturing process enters the era of 10 nanometers (nm), 5nm and even 3nm, the metal line width is getting smaller and smaller, and the layout structure of high aspect ratio makes it more difficult for PFA to analyze and locate manually

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