Semiconductor package structure and method for manufacturing the same
A packaging structure and semiconductor technology, which is applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., and can solve the problem of difficulty in executing the solder ball drop process.
Pending Publication Date: 2021-10-22
ADVANCED SEMICON ENG INC
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Problems solved by technology
However, the alignment marks are hidden by the pads and thus make the ball drop process difficult to perform
Method used
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[0032] Throughout the drawings and detailed description, common reference numbers are used to refer to the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
[0033] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed on the first feature. An embodiment in which a feature is fo...
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Abstract
A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
Description
technical field [0001] The present disclosure relates to a semiconductor package structure and a method, and to a semiconductor package structure including alignment marks. Background technique [0002] Traditionally, copper layers with special contours have been used as alignment marks in semiconductor packaging structures. However, the side surfaces of the alignment marks are not vertical planes, and therefore, the edges of the alignment marks may produce halos in charge-coupled device (CCD) images. There is also the use of specially contoured grooves, eg formed by etching a passivation layer, as alignment marks. However, the copper is exposed to air from the grooves, which oxidizes the copper to copper oxide, making it impossible for the CCD to recognize where the alignment marks are located. [0003] Additionally, bumps are built on the etched passivation layer using a plating process. Since the plating process involves warpage issues, thus reducing the process window...
Claims
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IPC IPC(8): H01L23/544H01L23/498H01L23/31H01L21/50H01L21/56
CPCH01L23/544H01L23/49838H01L23/3128H01L21/50H01L21/568H01L27/14618H01L27/14636H01L27/14683H01L2224/73267H01L2224/73204H01L2924/15311H01L2224/92244H01L2224/92125H01L2224/04105H01L2224/12105H01L2224/83132H01L2223/54426H01L2223/54486H01L2223/5442H01L21/56H01L21/6835H01L2221/68359H01L2221/68372H01L2221/68345H01L2224/16227H01L2224/32225H01L2224/214H01L2924/1434H01L2924/1433H01L2224/81005H01L2224/83005H01L25/0652H01L25/50H01L24/19H01L24/32H01L24/16H01L24/73H01L24/92H01L24/83H01L2224/16225H01L2924/00H01L23/3114H01L23/18H01L27/148H01L2224/05022H01L2924/181H01L2224/0401H01L24/05
Inventor 方绪南庄淳钧
Owner ADVANCED SEMICON ENG INC