Open-loop fractional frequency divider

Abstract

A cost-efficient and accurate open-loop fractional divider includes: an integer divider for processing an input clock according to a setting of a target frequency to generate a first divided clock and a second divided clock; the control circuit that is used for generating a coarse adjustment control signal and a fine adjustment control signal according to the setting of the target frequency; and the phase interpolator that is used for generating an output clock according to the first frequency division clock, the second frequency division clock, the coarse adjustment control signal and the fine adjustment control signal. The two groups of control signals determine a first current, and inverted signals of the two groups of control signals determine a second current; the phase interpolator controls the contribution of the first frequency-divided clock to the generation of the output clock according to the first frequency-divided clock and the inverted signal thereof, and the first current, and controls the contribution of the second frequency-divided clock to the generation of the output clock according to the second frequency-divided clock and the inverted signal thereof, and the second current.

Description

technical field [0001] The present invention relates to frequency dividers, and more particularly to open loop fractional frequency dividers. Background technique [0002] The current frequency division technology includes the following two types: [0003] (1) The first frequency division technology: such as figure 1 As shown, the technology utilizes a plurality of PLL circuits 110 (PLL1, PLL2, . . . , PLLN) to generate various clocks (CK1, CK2, . According to the design of the PLL circuits 110, the frequency of each of the various clocks can be an integer multiple or a non-integer multiple of the frequency of the reference clock. [0004] (2) The second frequency division technology: such as figure 2 As shown, the present technique includes a phase-locked loop circuit 210 (PLL1) and a plurality of open-loop dividers 220 (OPD2, . . . , OPDN). The PLL circuit 210 generates a clock (CK1) according to a known reference clock (XTAL). These open-loop dividers 220 respective...

AI Technical Summary

Problems solved by technology

[0005] Regarding the first frequency division technology, it uses multiple phase-locked loops, the overall circuit area is large, the cost is high, and the power consumption is high.

Regarding the second frequency division technique, when the frequency of each of the various clocks (CK2, ..., CKN) is a non-integer multiple of the frequency of the output clock, the frequency of the various clocks is usually not accurate enough

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