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Address translation cache invalidation in a microprocessor

A technology of address conversion and processor, applied in the field of processor

Pending Publication Date: 2021-12-24
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This disclosure is aimed at those of ordinary skill in the art

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  • Address translation cache invalidation in a microprocessor
  • Address translation cache invalidation in a microprocessor
  • Address translation cache invalidation in a microprocessor

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Embodiment Construction

[0018] The following description is made to illustrate the general principles of the invention and is not meant to limit the inventive concepts claimed herein. In the following detailed description, numerous details are set forth in order to provide an understanding of computer systems, computer architectures, processors, and methods of operation thereof, however, those skilled in the art will understand that computer systems, computer architectures, processors, and Various and many embodiments of methods of operation may be practiced without those specific details, and the claims and disclosure should not be limited to the embodiments, arrangements, components, subcomponents, systems, features, process, method, aspect, means and / or details. Further, certain features described herein can be used in combination with other described features in each of the different possible combinations and permutations.

[0019] Unless otherwise specifically defined herein, all terms are to b...

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Abstract

A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and / or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

Description

Background technique [0001] The present disclosure relates generally to processors, and more particularly to methods and systems for changing or removing address translations within an information handling system, including the handling of address translation invalidation instructions in systems with multiple processors. [0002] Conventional computers typically include multiple processors capable of storing different types of data, such as data used to translate virtual addresses to physical addresses. Data can be widely distributed and stored on different processors throughout the system. To improve virtual memory translation performance, most modern microprocessors implement some form of address translation cache or buffer. The most common hardware construct for memory translation is the Translation Lookaside Buffer (TLB). When an address translation for a virtual page is changed or removed, eg, due to page remapping or page replacement, the cache or buffer entry containi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00
CPCG06F2212/1024G06F12/1027G06F2212/657G06F12/10G06F12/0284G06F12/109G06F12/1036G06F12/0292
Inventor D.查特吉L.莱特纳B.科克罗夫特J.舒曼K.尤库姆
Owner IBM CORP