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Write verification circuit applied to STT-MRAM

A verification circuit and circuit technology, applied in the field of write verification circuits, can solve the problems of increased power consumption of write operations, large write operation time margin, etc., and achieve the effects of reducing power consumption and simplifying the process of writing operations

Pending Publication Date: 2022-01-28
JIANGNAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problem that the current write operation requires read operation verification and the write operation time margin is too large, resulting in increased write operation power consumption, the present invention provides a write verification circuit applied to STT-MRAM

Method used

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  • Write verification circuit applied to STT-MRAM
  • Write verification circuit applied to STT-MRAM
  • Write verification circuit applied to STT-MRAM

Examples

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Embodiment 1

[0062] This embodiment provides a write verification circuit applied to STT-MRAM, the circuit includes: a write operation completion detection circuit and a write self-termination circuit; the write operation completion detection circuit is used to determine whether the write operation is completed, and generate a detection Feedback signal COP; the write self-termination circuit generates a write operation signal and a write operation termination signal according to the detection feedback signal COP.

[0063] The write verification circuit of this embodiment is composed of a write operation completion detection circuit and a write self-termination circuit. The change of the write circuit in the STT-MRAM unit is detected by the write operation completion detection circuit, and the state of the write operation is monitored in real time. Once the write operation is detected, the feedback signal COP is immediately applied to the write self-termination circuit to turn off the write ...

Embodiment 2

[0065] This embodiment provides a write verification circuit applied to STT-MRAM, and a write operation verification function of STT-MRAM is realized by a write operation completion detection circuit and a self-write termination circuit.

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Abstract

The invention discloses a write verification circuit applied to an STT-MRAM, belonging to the technical field of computer storage. The circuit comprises a write operation completion detection circuit and a write self-termination circuit, wherein the write operation completion detection circuit is used for judging whether write operation is completed or not and generating a detection feedback signal COP; the write self-termination circuit generates a write operation signal and a write operation termination signal according to the detection feedback signal COP. According to the write operation completion detection circuit, the state of write operation is monitored in real time according to the change of the state of the STT-MRAM in a write operation process, a detection feedback signal is generated to act on the write self-termination circuit, and once it is detected that the write operation is completed, the write self-termination circuit timely generates a write drive circuit termination signal, closes a write drive and ends the write operation; and with the write verification circuit, an write operation process is simplified, the write drive can be closed in time after the write operation is completed, and compared with traditional write operation, power consumption can be reduced by 50%.

Description

technical field [0001] The invention relates to a write verification circuit applied to STT-MRAM, which belongs to the technical field of computer storage. Background technique [0002] Spin-transfer torque random magnetic memory (STT-MRAM) is a new type of non-volatile memory, which is considered to be one of the new types of memory with the most potential to replace Flash. When writing data into the STT-MRAM memory, it is necessary to determine the direction of the write current according to whether the written data is "0" or "1". Then a write current is injected into the designated memory cell, so that the free layer in the MRAM memory cell is deflected, thereby causing a change of the storage state. Since the write operation mechanism of STT-MRAM is random in nature, in the case of constant physical characteristics, the flipping delay of its important device STT-MTJ unit is different at each write attempt. And for a constant current density, the writing process require...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/16
CPCG11C11/1677G11C11/1675
Inventor 姜岩峰成关壹
Owner JIANGNAN UNIV
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