Method for online upgrading of multiple FPGAs by main CPU
A technology of target code and bit computer, applied in the field of online upgrade of main CPU to multiple FPGAs, can solve problems such as complex operation, achieve the effect of improving upgrade efficiency and simplifying on-machine upgrade work
Pending Publication Date: 2022-02-08
SUZHOU CHANGFENG AVIATION ELECTRONICS
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[0003] In view of this, the embodiment of the present application provides a method for online upgrade of multiple FPGAs by the main CPU, through the data distribution of the main CPU to the upper computer, the online upgrade function of all FPGAs inside the product is realized, and the need for on-board display FPGA upgrades is solved. Each veneer needs to be disassembled, which is complicated and may introduce other risks
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[0025] Embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.
[0026] Embodiments of the present application are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. The present application can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all...
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The invention provides a method for a main CPU to upgrade multiple FPGAs online, and belongs to the technical field of military aviation display control, and the method specifically comprises the steps that the main CPU receives and analyzes an erasure instruction, and sends the erasure instruction to the corresponding FPGAs according to different erasure target boards; each FPGA performs an erasing operation on a specified FLASH which needs to be subjected to program burning at present according to the erasing instruction, and returns an erasing completion instruction to the main CPU; the main CPU analyzes the erasure completion instruction and returns the erasure completion instruction to the upper computer; the upper computer issues a burning target code to the main CPU; the main CPU receives the target code and forwards the target code to the corresponding FPGA; the corresponding FPGA carries out FLASH data burning, and after data burning is completed, a current data packet burning ending instruction is returned to the main CPU; after the main CPU receives a current data packet burning ending instruction of the FPGA, the upper computer is commanded to continue to send a next target code; and repeating the steps until the target code is completely burnt. Through the processing scheme provided by the invention, the FPGAs in the product are upgraded at the same time, the on-board upgrading work is simplified, and the upgrading efficiency is improved.
Description
technical field [0001] The present application relates to the field of military aviation display control technology, in particular to a method for online upgrading of a main CPU to multiple FPGAs. Background technique [0002] At present, in the field of domestic military aviation, airborne large-screen displays are generally composed of multiple module boards, including a main CPU and multiple FPGAs. Among them, the main CPU mainly completes the communication control between the display and external cross-linking equipment, including using RS422, ARI NC429, 1553B, optical fiber and other bus methods, and at the same time completes data interaction with multiple FPGAs through the RS232 serial port. FPGA mainly completes the functions of assisting communication, video display, etc. As an auxiliary extension of the main CPU, it has the characteristics of superior performance and flexible use. However, in the process of airborne use, when the internal CPU and FPGA of the produ...
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IPC IPC(8): G06F8/65G06F8/61
CPCG06F8/65G06F8/61
Inventor 丁露刘宁王文凯李子路
Owner SUZHOU CHANGFENG AVIATION ELECTRONICS