Apparatus and method for speculatively vectorizing program code

Abstract

An apparatus and method for speculatively vectorizing program code are provided. The apparatus includes processing circuitry to execute program code, the program code including an identified code region, the identified code region including at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorization of a series of scalar memory access operations using a plurality of processing lanes. The trace storage is to maintain trace information for each speculative vector memory access instruction, the trace information providing an indication that a memory address is accessed within each lane. Checking circuitry then refers to the trace information during execution of the identified code region by the processing circuitry in order to detect any inter-channel memory hazards resulting from the execution of the plurality of speculative vector memory access instructions. For at least a first type of inter-channel memory hazard, a status storage element is used to maintain an indication of each channel for which the check circuitry has determined that the type of memory hazard exists. The playback determination circuit is then arranged to, upon reaching an end of the identified code region, trigger a re-execution of the identified code region for each channel identified by the state storage element in response to the state storage element identifying at least one channel as having an inter-channel memory hazard. Such methods may significantly increase the ability to vectorize scalar codes, resulting in a significant improvement in performance.

Description

Background technique [0001] The technology relates to apparatus and methods for speculative vectorization of program code. [0002] In seeking to improve performance, vector processing circuits have been developed that enable multiple operations to be performed in parallel in the multiple processing lanes provided by the vector processing circuits. In association with such vector processing circuits, vector instruction set architectures (ISAs) have been developed that provide new instructions and wider data paths. For example, single instruction multiple data (SIMD) vector processing circuits include multiple processing elements that can simultaneously perform the same operation on multiple different data sets in order to take advantage of data-level parallelism. Thus, a single vector instruction may specify one or more vectors of input data values, where the input data values ​​within each vector are processed within corresponding parallel processing lanes within the vector ...

AI Technical Summary

Problems solved by technology

In practice, the limitations of the compiler's memory aliasing analysis and the presence of infrequent memory data dependencies mean that entire regions of code cannot be safely vectorized in existing systems without risking changing the semantics of the application, thus limiting the achievable usable performance increase

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