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Single event upset resistant latch circuit

An anti-single-event, flip-lock technology, applied in logic circuits, electrical components, generating electrical pulses, etc., can solve problems such as slow data transmission in circuits, and achieve the effect of single-event immunity

Pending Publication Date: 2022-05-24
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention provides an anti-single-event flipping latch circuit, which solves the technical problem of slow circuit data transmission speed while the single-event reinforcement of the latch is strengthened

Method used

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  • Single event upset resistant latch circuit

Examples

Experimental program
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Embodiment Construction

[0046] The embodiment of the present invention solves the technical problem of slow data transmission speed when the latch is hardened by a single event by providing an anti-single event flipping latch circuit.

[0047] In order to better understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0048] First of all, the term "and / or" that appears in this article is just an association relationship that describes associated objects, which means that there can be three relationships, for example, A and / or B, which can mean: there is A alone, and A exists at the same time and B, there are three cases of B alone. In addition, the character " / " in this article generally indicates that the contextual objects are an "or" relationship.

[0049] like figure 2 As shown, a common unhardened latch circuit includes a first inverter, ...

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Abstract

The invention discloses an anti-single event upset latch circuit. The anti-single event upset latch circuit comprises a first phase inverter, a first gated phase inverter, a second gated phase inverter and a first delay element, the first delay element is connected to the branch where the first phase inverter in the latch feedback loop is located, when the latch enters the data transmission stage, the first delay element fails, loads cannot be increased, and the data transmission speed cannot be reduced; when the latch enters a data retention stage, the first delay element is effective, and latch of error level is avoided based on the load delay characteristic of the first delay element, so that single-particle immunity is realized.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an anti-single event reversal latch circuit. Background technique [0002] In the radiation environment of digital circuit chips, external incident charged particles will cause ionizing radiation, and a certain number of electron-hole pairs will be generated around the trajectory of the particles. When there are enough electron-hole pairs deposited along the incident direction of the particles, The current induced by the electron-hole pairs collected by the depletion layer will cause the flipping of the drain level, forming a single event flipping. The level that occurs in the combinational logic unit is restored with the end of the single event flip; when the particle flip occurs in the sequential logic unit (such as flip-flop, latch, etc.) or the memory storage array, due to the existence of the feedback structure in the storage unit , the flip is locked and the le...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/003H03K3/356
CPCH03K19/00338H03K3/356017
Inventor 刘海南韩郑生闫珍珍杨婉婉卜建辉郭燕萍许婷高立博王成成赵发展
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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