FPGA (Field Programmable Gate Array) SRAM (Static Random Access Memory) configuration circuit architecture based on relay circuit and FPGA

Abstract

According to the FPGA SRAM configuration circuit architecture based on the relay circuit and the FPGA, the FPGA SRAM configuration circuit architecture comprises a word line control circuit, a word line driving circuit, a bit line control circuit and a bit line driving circuit, the bit line driving circuit divides a driven SRAM array, the load of each section of driving circuit is reduced, a plurality of SRAM array areas are formed, and the SRAM array area is divided into a plurality of SRAM array areas; through mutual cooperation of the bit line control circuit and the word line control circuit, the bit line of each SRAM array area is jointly driven by the bit line driving circuits on the two sides, meanwhile, for a segment of segmented bit line, the bit line driving circuit is jointly driven by the driving circuits on the two sides, and compared with single-side driving in the prior art, the driving capacity is higher. Therefore, the write-in success rate of the SRAM array can be effectively improved, and the product reliability is improved; and meanwhile, after the SRAM array is expanded, direct multiplexing expansion is easy, the problem of driving capability does not need to be considered any more, and the design verification cost can be saved.

Description

technical field [0001] The invention belongs to the technical field of FPGA, and in particular relates to a relay circuit-based FPGA SRAM configuration circuit architecture and an FPGA. Background technique [0002] FPGA is an important device in the field of integrated circuits. It performs functional configuration by receiving a set of specific configuration data. Different configuration data can enable FPGA to achieve different functions. The configuration data is stored in the SRAM array of the FPGA, so ensuring that the SRAM array is successfully written is critical for the FPGA to implement various functions. [0003] The FPGA SRAM configuration circuit architecture and its excellent performance are necessary conditions for the success of SRAM array writing. The SRAM write operation needs to open the SRAM word line, and at the same time the bit line driver controls the bit line to be set to the data value to be written. The SRAM read operation is the basic way to ver...

AI Technical Summary

Problems solved by technology

Due to the above factors, the voltage received by the SRAM unit cannot meet the requirements for correct writing, and the SRAM cannot be written correctly, which ultimately affects the function of the FPGA.

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