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Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line

A technology of branch target address and target address, which is applied in the field of branch instructions, can solve problems such as complex situations, and achieve the effect of avoiding branch loss and improving branch performance

Inactive Publication Date: 2002-09-18
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, the situation is complicated by the fact that variable-length instructions are executed in the processor, so branch instructions may involve crossing two high-speed wires.

Method used

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  • Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line
  • Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line
  • Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line

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Embodiment Construction

[0032] now refer to figure 1 , which is a block diagram of a microprocessor 100 with a pipeline according to the present invention. Microprocessor 100 includes a number of stages from 101 to 132 . In one embodiment, the microprocessor 100 includes an x86 architecture processor.

[0033] The first stage of the pipeline processor 100 is the instruction cache generation stage or C stage 101 for short. The C stage 101 generates the fetch address 162 used to select a high-speed line in the instruction cache 202 (see FIG. 2).

[0034] The next stage is the I stage 102, or the instruction fetch stage. In order to fetch instructions to the pipeline processor 100 for execution, the I stage 102 provides the stage for the pipeline processor 100 to fetch the address 162 to the instruction cache 202 (see FIG. 2 ). The instruction cache 202 will be described in more detail with reference to FIG. 2 . In one embodiment, the instruction cache 202 is a two-cycle cache. Stage B 104 is the ...

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Abstract

A branch control device in a microprocessor. The device includes a branch target address cache for high-speed indication of whether branch instructions span two high-speed lines. When the instruction cache fetching address of the first high-speed line containing the first part of the branch instruction is entered into the branch target address cache, the branch target address cache will output the target address of the branch instruction and show the coverage status. The target address is stored in the register. The next sequentially fetched address selects the second high speed line containing the second portion of the branch instruction. After fetching the two high speed lines containing the branch instruction, in order to fetch the third high speed line containing the target instruction of the branch, the target address from the cache is sent to the instruction cache. The three high-speed lines are sequentially stored in the instruction buffer for decoding.

Description

technical field [0001] The present invention is in the field of branch target address high speeds in microprocessors, and more particularly relates to a branch instruction covering spanning instruction high speed lines. Background technique [0002] A microprocessor includes multiple pipeline stages, and each stage fulfills different functional requirements in the execution of program instructions. The functions of the pipeline stages are usually instruction fetch, instruction decode, instruction execution, memory access and result write-back. [0003] The instruction fetch phase is to fetch the next instruction in the currently executing program. The next instruction is typically the instruction with the next consecutive memory address. However, as far as the branch instruction is taken, the next instruction is the instruction of the memory address specified by the branch instruction, which is usually used as a reference of the branch target address. The instruction fetc...

Claims

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Application Information

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IPC IPC(8): G06F9/00G06F9/42G06F12/02
Inventor 布兰特比恩G·葛兰亨利汤玛斯C·麦当劳
Owner IP FIRST
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