Semiconductor memory device

Abstract

A semiconductor memory device is capable of simultaneously reading data and refreshing data and checking whether a data restoring function is operating normally. A data inputting circuit receives datainputted from an external circuit. A parity generating circuit generates parity data from the data input from the data inputting circuit. A memory stores the data input from the data inputting circuit and the parity data generated by the parity generating circuit. A refreshing circuit refreshes the memory. A reading circuit reads the data from the memory. A restoring circuit restores data to be refreshed by the refreshing circuit from other data read normally and corresponding parity data, while the reading circuit is reading data. A data outputting circuit outputs the data read by the reading circuit and the data restored by the restoring circuit. A parity outputting circuit directly reads and outputs the parity data stored in the memory.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of simultaneously reading data and refreshing data. Background of the invention [0002] Because DRAM (Dynamic Random Access Memory) requires refreshing of memory cells, it is common practice to temporarily disable access from external circuits while memory cells are being refreshed. [0003] Temporary prohibition of access to the DRAM from external circuits constitutes a disadvantage of the DRAM, especially when high-speed access is required, because the temporary prohibition of access prolongs the response time of the access. [0004] In view of the above disadvantages, the applicant filed a patent application (hereinafter referred to as "semiconductor memory device disclosed in the filed application") (Japanese Patent Application No. 2000-368423) related to a semiconductor memory device, and even when the device The device ...

AI Technical Summary

Problems solved by technology

[0036] The semiconductor memory device disclosed in the filed application has a disadvantage in that, since the parity data stored in the parity unit 11 cannot be directly read and written, it is difficult to determine the parity unit 11 and the function related thereto, that is, data recovery Whether the function is normal

[0037] The problem with the semiconductor memory device disclosed in the filed application is that, when the data stored in the DQ0-DQ3 cells 12-15 is read, since the data is restored from the parity data according to the refresh operation, the stored data cannot be read directly, making it difficult to perform operational checks

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