Semiconductor device

Abstract

To improve the lack of an operating margin and an operation failure caused by signal wiring laid between circuit blocks without replacing a mask after a chip is inspected. A logic circuit block 11 and a memory circuit block 12 are provided to a semiconductor chip 10, and a timing control circuit block 13 controlling the transmission timing of signals is provided to an interconnect line between the circuit blocks 11 and 12. The timing control circuit 30 is composed of a delay element block 31 equipped with a plurality of delay elements A, B, and C giving different amounts of delay to inter-block signals DA1, a counter circuit block 32 which receives timing regulating / controlling signals CNT from the timing control circuit block 13, and a fuse circuit block 33 which is fused on the basis of fuse information signals FO possessed by the counter circuit block 32 and has the substantial same function with the counter circuit block 32.

Description

Technical field [0001] The present invention relates to a semiconductor device having a plurality of circuit blocks with different functions formed on a chip. Background technique [0002] In recent years, people are working hard to develop a system LSI that mixes a logic circuit and a memory circuit on a single chip, with the goal of improving the performance of the system. [0003] In the layout design process, the wiring between the logic circuit and the memory circuit formed on the chip starts from determining the layout of each circuit on the chip, and through the use of various layout and wiring tools , As far as possible, do not occur due to the deviation of the wiring width and wiring length, the phenomenon of crosstalk caused by the signal staggered operation caused by the phenomenon. [0004] Such as Figure 16 As shown, in the chip inspection process, the wiring between the first circuit block 101 and the second circuit block 102 formed on the chip 100 is inspected by ...

AI Technical Summary

Problems solved by technology

As a result, the increase in wiring length, small changes in individual wiring lengths become non-negligible factors due to reduced operating margins

[0007] In addition, the operating tolerance of the circuit is also reduced due to new factors such as the power supply voltage drop in the chip, so that it is more difficult to adjust the signal between circuit blocks when designing the chip.

[0008] Also, when inspecting or evaluating the above-mentioned conventional semiconductor device, even if it is possible to determine the malfunction caused by the propagation timing of the signal, there is no means to determine the defect, and even if the place to be corrected can be fixed, It is also necessary to change the mask, so it is difficult to shorten the development time and reduce the development cost

[0009] The present invention was developed to solve the existing problems, and its purpose is to improve the insufficient operating margin and malfunction caused by the signal wiring between circuit blocks without changing the mask after the chip is inspected.

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