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Device and method for preventing stagnation of microprocessor pipeline

A microprocessor and pipeline technology, applied in the field of microelectronics, can solve problems such as large access delays

Active Publication Date: 2005-01-26
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Implementing these changes often requires a microcode ROM with a larger capacity or entry size, and a ROM that provides these larger attributes will suffer from a larger access delay

Method used

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  • Device and method for preventing stagnation of microprocessor pipeline
  • Device and method for preventing stagnation of microprocessor pipeline
  • Device and method for preventing stagnation of microprocessor pipeline

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0034] In view of the above background discussion of instruction translation and corresponding techniques used in current pipeline microprocessors for generating microinstruction sequences, a more detailed discussion of the problems addressed by the present invention will be presented in conjunction with figure 1 , figure 2 to proceed. Immediately thereafter, the discussion of the present invention will cooperate with Figure 3 to Figure 5 And manifested. The present invention can effectively absorb the delay caused by the microcode ROM access delay when the verification logic for accessing the corresponding microcode ROM sends the microinstruction before the corresponding microcode entry point is sent to the next pipeline stage. caused pipeline stagnation.

[0035] refer to figure 1 , the block diagram shown is a block diagram illustrating stages of an embodiment within a current microprocessor. Microprocessor 100 includes eight example stages 101 - 108 : fetch stage 10...

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Abstract

An apparatus and method are provide for precluding stalls in a microprocessor pipeline due to microcode ROM access delay. The apparatus includes a micro instruction queue and early access logic. The micro instruction queue provides a plurality of queue entries to register logic. Each of the plurality of queue entries includes first micro instructions and a microcode entry point. All of the first micro instructions correspond to an instruction. The microcode entry point is coupled to the first micro instructions. The microcode entry point is configured to point to second micro instructions stored within a microcode ROM. The early access logic is coupled to the micro instruction queue. The early access logic employs the microcode entry point to access the microcode ROM prior to when the each of the plurality of queue entries is provided to the register logic, whereby a first one of the second micro instructions is provided to the register logic when the first one of the second micro instructions is required by the register logic.

Description

technical field [0001] The present invention relates to the field of microelectronics, and more particularly to an apparatus and method for preventing stalls in the pipeline of a microprocessor due to delays in accessing microcode ROMs. Background technique [0002] Today's microprocessors are used to execute applications that include a series of instructions, and these instructions conform to a specific instruction set architecture (ISA). For example, an x86 compatible microprocessor executes an application program that has been coded using instructions conforming to the x86 ISA. These instructions are generally stored in memory and are retrieved when required by the microprocessor for execution. [0003] The types of operations specified by means of instructions taken from any known ISA and their corresponding complexities are quite diverse. At one extreme, an instruction to complement the contents of a register requires the microprocessor to perform a single, simple ope...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G11C16/08
CPCG06F9/267G06F9/28
Inventor G·葛兰·亨利弟尼斯·K·詹泰瑞·派克斯
Owner IP FIRST
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