Technique for interconnecting multilayer circuit boards
A multi-layer circuit board and circuit technology, which is applied in the direction of multi-layer circuit manufacturing, circuit, structural connection of printed circuit, etc., can solve problems such as noise, increased circuit module cost of multi-connected PCB, increased energy consumption, etc.
Inactive Publication Date: 2010-04-21
NORTEL NETWORKS LTD
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- Description
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- Application Information
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Problems solved by technology
In many cases, these connectors introduce parasitic capacitance, parasitic resistance, parasitic inductance, electromagnetic interference (EMI), noise, increased energy consumption, etc., which typically lead to attenuation of signal propagation between PCBs
In addition, the use of connectors usually greatly increases the cost of producing circuit modules with multi-connected PCBs
In addition, traditional connection techniques cannot take advantage of the benefits brought by circuit boards using channel routing
Method used
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Embodiment Construction
[0017] Figure 1A-3 Various typical techniques for connecting two or more PCBs using double-sided pin devices are described. Figure 1A and 1B A typical technique is described using double-sided via-based pin devices, such as pin grid array (PGA) cards, to connect two PCBs, where at least one of the PCBs incorporates vias of different depths. Figure 2A and 2B Describes a typical technique for connecting two PCBs using a double-sided mixed-pin device, at least one of which incorporates vias of different depths. The term mixed-pin device typically refers to a circuit device that uses through-hole based pins (such as PGA) and surface mount (SMT) pins (such as column grid array (CGA) or ball grid array ( BGA)). image 3 Two PCBs connected by a double-sided pin arrangement of a subset of pins of the same length are described. Although Figure 1A-3 A typical embodiment is described with a double-sided pin arrangement for connecting two PCBs, each with vias of different depths ...
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A circuit device for interconnecting first and second multilayer circuit boards is described herein. The first multilayer circuit board may include a first plurality of electrically conductive vias ofvarying depths and the second multilayer circuit board may include a second plurality of electrically conductive vias. The circuit device comprises a first plurality of pins located on a first side ofthe circuit device corresponding to the first plurality of electrically conductive vias of the first multilayer circuit board, each pin having a length compatible with a depth of a respective one oft he first plurality of electrically conductive vias of the first multilayer circuit board. The circuit device further comprises a second plurality of pins located on a second side of the circuit devicecorresponding to the second plurality of electrically conductive vias of the second multilayer circuit board.
Description
technical field [0001] The present invention relates generally to connecting multiple circuit boards, and more particularly to techniques for interconnecting two or more multilayer circuit boards having vias of different depths. Background technique [0002] The inherent limitations of single signal layer printed circuit boards (PCBs) led to the development of multilayer PCBs. This multilayer PCB can be single-sided or double-sided, or it can have multiple signal layers on the surface of the multilayer PCB and be buried in the multilayer PCB. [0003] While a multilayer PCB has a theoretically unlimited number of layers, problems can arise when there are more than a reasonable number of layers in a multilayer PCB, especially when trying to route high-speed electronic signals between routing electronic components. For example, conductive vias are often used when making electrical connections between different layers in a multi-layer PCB. While these conductive paths allow d...
Claims
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IPC IPC(8): H05K3/40H05K3/36H05K1/11H01R13/66H01R12/04H01R12/16H01R12/51H01R13/642H05K1/14H05K3/34H05K3/42H05K3/46
CPCH05K3/429H05K2201/10659H01R13/642H05K2201/09472H05K3/365H05K2203/061H05K3/368H01R12/57H05K3/3447H01R12/523H01R13/665H05K2201/09536H05K3/3436Y10T409/300112Y10T409/300616H05K1/14H05K3/46
Inventor 赫尔曼·邝阿内塔·瓦兹约克斯卡琉吉·迪费里波
Owner NORTEL NETWORKS LTD