Methods for forming structure and spacer and related FINFET

Abstract

This invention relates to methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124) , and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

Description

technical field [0001] The present invention generally relates to CMOS processes. Background technique [0002] Isolation layers are provided in complementary metal-oxide-semiconductor (CMOS) processes to protect common structures of one structure from processes performed on adjacent structures. Exemplary types of CMOS devices in which protective isolation layers must be used are Fin Field Effect Transistors (FinFETs) and MesaFETs. For example, a FinFET structurally includes, among other things, a gate on and extending along a portion of each sidewall of a thin, vertical silicon "fin." In FinFETs, isolation layers are required to block implants at the gate edge and to prevent silicide from shorting to the gate. Conventional planar CMOS spacer processes have many problems related to fins. In particular, the conventional process of forming an isolation layer for a gate leads to the application of fins. Fin erosion during spacer etch is a potential problem if conventional s...

AI Technical Summary

Problems solved by technology

The same problem exists in other CMOS devices involving e.g. MesaFET

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