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System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links

一种数据包、完成数据包的技术，应用在数字传输系统、传输系统、数据交换网络等方向，能够解决消耗计算机系统总线带宽总线吞吐率等问题

Active Publication Date: 2007-04-25
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] These packets consume a large amount of bus bandwidth of a computer system employing a PCIe link and limit the bus throughput of said system

Method used

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  • System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links
  • System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links
  • System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links

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Embodiment Construction

[0031] Embodiments of the invention provide methods and systems for communication in computer systems employing peripheral component interconnect express (PCIe) links. PCIe is a general-purpose input / output (I / O) interconnect used for communication between two or more devices within a computer. The devices may include one or more endpoint devices and a chipset.

[0032] FIG. 1 is a block diagram illustrating an environment 100 (which is exemplary, such as a computer system, within which embodiments of the invention may function). Environment 100 includes a chipset 102 , an endpoint device 104 and an endpoint device 106 . Those skilled in the art will readily appreciate that the number of endpoint devices does not limit the invention in any way.

[0033] Chipset 102 is a root complex, such as a chipset, that includes chips commonly known as Northbridge and Southbridge in communication with at least one of Endpoint Device 104 and Endpoint Device 106, a Central Processing Unit ...

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PUM

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Abstract

A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.

Description

technical field [0001] The present invention relates generally to communication of computer systems. More particularly, the present invention relates to a method and system for communications in a computer system employing a peripheral component interconnect express (PCIe) link. Background technique [0002] Peripheral Component Interconnect Express (PCIe) is a general-purpose input / output (I / O) interconnect used for communication between two or more devices within a computer. Examples of such devices may include a graphics processor and a chipset. Computer systems using PCIe communicate by sending packets of data. Data packets are formed in three discrete logical layers including a processing layer, a data link layer and a physical layer. Each data packet has a header corresponding to these layers and a data payload section. The header contains information which may include packet format, type and attributes, address / routing information, encoding information and data pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/06H04L12/56
CPCY02B60/1235Y02B60/1228G06F13/4022Y02D10/00
Inventor 威廉·P·朱
Owner NVIDIA CORP
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