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Pattern density control method using edge printing processes

A manufacturing method and process technology, applied in the field of pattern density control, can solve problems such as changes in polishing and internal etching steps, etc.

Inactive Publication Date: 2007-05-09
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, polishing and etch-back steps may vary due to pattern density variations on the wafer

Method used

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  • Pattern density control method using edge printing processes
  • Pattern density control method using edge printing processes
  • Pattern density control method using edge printing processes

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Embodiment Construction

[0009] 1-8C show cross-sectional views of a structure 100 undergoing fabrication steps of a subtractive sidewall image transfer (SIT) process, according to an embodiment of the invention. More particularly, referring to FIG. 1, in one embodiment, as shown, the SIT process begins with a semiconductor substrate 110, a gate dielectric layer 120, a gate electrode layer 130, a hard mask layer 140, a memory layer 150, And the alignment layers 160 are formed one by one thereon. For example, layers 110, 120, 130, 140, 150 and 160 are made of silicon (Si), silicon dioxide (SiO 2 ), polysilicon, silicon nitride, polysilicon, and silicon dioxide.

[0010] Next, referring to FIG. 2 , in one embodiment, a patterned photoresist layer 210 is prepared over the oxide alignment layer 160 by, for example, a photolithographic process.

[0011] Next, referring to FIG. 3 , in one embodiment, the oxide positioning layer 160 ( FIG. 2 ) is directionally etched through the patterned photoresist layer...

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Abstract

A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.

Description

technical field [0001] The present invention relates to pattern density control, and more particularly to pattern density control using edge printing processes. Background technique [0002] In a conventional sidewall image transfer (SIT) process, the storage region is formed from the storage layer, which is then used as a mask to etch one or more layers below the storage region in order to transfer the image of the storage region to the underlying layer. Forming the memory region from the memory layer involves polishing and etch-back steps. However, there may be variations in the polishing and etch-back steps due to variations in pattern density on the wafer. Therefore, pattern density control methods are needed in sidewall image transfer (SIT) technology and other edge printing processes. Contents of the invention [0003] The present invention provides a structure manufacturing method, including providing a design structure, which includes (i) a design substrate, (ii...

Claims

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Application Information

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IPC IPC(8): G03F7/20H01L21/027
CPCH01L29/66545H01L27/1052Y10S438/95H10B99/00
Inventor 戴维·V.·霍拉克查尔斯·W.克伯格三世古川俊治马克·C.·哈克斯蒂芬·J.·霍姆斯
Owner IBM CORP
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