CMOS single stabilization circuit

Abstract

This invention relates to one CMOS signal stable circuit, which comprises integral circuit, three status circuit and its control circuit and logic output circuit, wherein, the control circuit generates control signals with input end, zero clear end and output end; the three status control circuit adopts two Smite trigger for sample on integral circuit to generate three status circuit needed control signals by sample result; the two Smite trigger generates output signals through logical computation.

Description

technical field [0001] The invention relates to a CMOS monostable circuit, which can be widely used in applications such as pulse shaping, time delay and timing. Background technique [0002] The salient feature of a monostable circuit is that it has two different working states: steady state and transient state. Under the action of an external trigger pulse, it can turn from a steady state to a temporary steady state, and after the temporary steady state is maintained for a period of time, it will automatically return to the steady state. The duration of the transient steady state depends on the parameters of the circuit itself, and has nothing to do with the amplitude of the trigger pulse. Generally speaking, a monostable circuit is composed of an integrating circuit, a tri-state gate and a tri-state gate control circuit. The output of the monostable circuit is directly determined by the result of the integral circuit, and the control signal of the tri-state gate control...

AI Technical Summary

Problems solved by technology

Therefore, the existing monostable circuit has the disadvantages of poor anti-interference ability and low reliability.

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