Leakage current reduction method

Abstract

The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Description

FIELD OF THE INVENTION [0001] The present invention relates to electronic circuitry and, in particular, to a leakage current reduction method. BACKGROUND OF THE INVENTION [0002] In a prior approach for powering down a circuit system, when the system goes into sleep / data retention mode, the main power supply VDD goes from 1.3V (in active mode) to near 0V, a retaining power supply VRET remains unchanged at, for example, 1.3V, a retain signal RET goes from 0V to VRET (1.3V) level, and some internal nodes of the system are raised to a reference voltage VBB level (for example 0.6V). [0003] For circuits whose data needs to be retained when the system goes into sleep / data retention mode, the typical way of turning off the P Channel (PCH) device is shown below: [0004] Vdrain=VBB (0V-->0.6V, for example) [0005] Vgate=RET (0-->1.3V, for example) [0006] Vsource=VDD (1.3V-->0V, for example) [0007] Vbulk=VRET (1.3V, for example) [0008] This is demonstrated in the wordline circuit shown ...

AI Technical Summary

Benefits of technology

[0010] A method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Problems solved by technology

The problem with this prior art solution is that large voltage differences between the gate (1.3V) and the source (0V) / drain (0.6V) exist which results in large gate tunneling leakage, which dominates the P channel device leakage at room temperature since the sub-threshold leakage is suppressed by the deep back-gate bias.

This leads to high standby power consumption.

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