Chip packaging structure
a technology of chip packaging and chip shell, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of limited 610 mm610 blank (before cutting) of organic substrate, limited trace width and trace pitch currently available inside the substrate, and insatisfactory current demands, etc., to achieve the effect of increasing the circuit layout density of multi-layer interconnection structure and higher electrical performan
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second embodiment
[0035] As described above, the chip packaging process of the invention therefore economically uses a stiffener substrate that, associated with a heat sink, reinforce the mechanical strength of the package structure and further promote heat dissipation through the heat sink. Alternatively, a single heat sink provided with a cavity may be substituted for the above association of a stiffener substrate and a heat sink as described in the following second embodiment of the invention.
[0036] Reference now is made to FIG. 3A through FIG. 3D to describe a chip packaging process according to a second embodiment of the invention. It should be noticed that only the processing steps particular to this second embodiment are illustrated, and the description of the processing steps common to the first and second embodiments are omitted.
first embodiment
[0037] As illustrated in FIG. 3A, an isolating layer 304 and a multi-layered interconnection structure 306 are sequentially formed on a base substrate 302, and a chip 314 is flip-chip mounted on the top surface 306a of the structure 306, similar to the A heat sink 342, having a cavity 344, is attached on the top surface 306a via an adhesive layer 330, with the cavity 344 facing down to receive the chip 314 therein. The heat sink 342 is preferably made of a material having good thermal conduction such as copper or aluminum. The adhesive layer 330 includes a plurality of conductive vias 332 that connect the conductive traces inside the structure 306 to the heat sink 342. If the heat sink 342 is electrically conductive, a power reference or ground reference can be thereby provided.
[0038] A sealing compound 346 is filled in the gaps between the chip 314 and the structure 306 and the gaps between the chip 314 and the inner sides of the cavity 344 to prevent a popcorn effect.
[0039] Refe...
third embodiment
[0042] Referring to FIG. 4, a schematic view illustrates a packaging structure according to the invention. As illustrated, a chip module 414 is packaged in the packaging structure. The chip module 414 includes a plurality of chips 414a, 414b that are flip chip mounted on the multi-layered interconnection structure 406 and electrically connected through its inner circuit. The chips 414a, 414b are thereby interconnected through the inner circuits of the multi-layered interconnection structure 406, and can therefore form a multi-chip module (MCM) or a system in package (SIP).
[0043] As described above, the invention therefore provides a chip packaging comprising a flexible interconnection structure, at least one chip, a stiffener layer and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and the inner electrical circuits electrically connected to the bumps and the contact termin...
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