Decoding circuit and decoding method for a Viterbi decoder

Abstract

The invention provides a decoding circuit and a decoding method for a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

Description

[0001] This application is a Continuation of co-pending application Ser. No. 10 / 020,160, filed on Dec. 18, 2001, and for which priority is claimed under 35 U.S.C. § 120; and this application claims priority of Application No. 089127633 filed in Taiwan, R.O.C. on Dec. 22, 2000 under 35 U.S.C. § 119; the entire contents of all are hereby incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to a decoding circuit and a decoding method for a Viterbi decoder in a Partial Response Maximum Likelihood (PRML) system of an optical disc. Particularly, the invention relates to a decoding circuit and a decoding method for a Viterbi decoder in a PRML system of an optical disc wherein a run length limited code (RLL Code) is used for effectively simplifying the complicated trellis diagram of the Viterbi decoder after longitudinal arrangement without a lot of registers for data processing. [0004] 2. Description of the Related Art [0005] I...

AI Technical Summary

Benefits of technology

[0021] It is therefore an object of the invention to provide a decoding circuit and a decoding method for a Viterbi decoder capable of solving the complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

[0025] Consequently, the invention provides a decoding circuit and a method for a Viterbi decoder. In this invention, a RLL code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. Therefore, the ACS can perform adding and comparing operations in parallel, and the register array can perform other operations at different time. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing in the ACS and PMU.

Problems solved by technology

Since a feedback loop exists in the ACS unit (the survivor metric of each state has to be re-calculated), it is difficult to implement a high-speed Viterbi decoder.

First, the decoding hidden path is too long.

Second, if the path is too long, the capacity of the hardware for recording will be relatively great (the hardware is called a path memory unit).

However, in the actual implementation, it is not possible to perform such a trace-back operation for finding each root.

The disadvantage of the trace-back method is that it is usually implemented using RAMs.

Thus, it is allowable for the application of DVD players but is not allowable in DVD ROMs due to its slow speed.

If registers are used for increasing the speed, a lot of hardware costs should be paid because four blocks are processing the data simultaneously in the trace-back method.

Thus, this method is not suitable for high-priced memories.

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