Semiconductor device and method for fabricating the same
a technology of semiconductors and semiconductors, applied in the field of semiconductor devices, can solve the problems of most point defects, which have been created in excessive numbers, and achieve the effect of reducing leakage current and enhancing diffusion
Inactive Publication Date: 2006-09-14
PANASONIC CORP
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Benefits of technology
"The present invention provides a semiconductor device and a method for fabricating it that can shallow the junction depths of extended high-concentration dopant diffused layer and pocket dopant diffused layer while minimizing junction leakage current. The device includes a gate electrode, a pocket dopant diffused layer, and a dislocation loop layer. The method includes steps of forming an amorphous layer, implanting heavy ions, and conducting an annealing process. The use of heavy ions with a large mass number can achieve pre-amorphization effects and trap silicon interstitials, resulting in a shallower junction. The method also reduces leakage current and segregates parts of the dopant diffused layer, contributing to the miniaturization of the transistor."
Problems solved by technology
In addition, most of point defects, which have been created in excessive numbers due to the damage involved with implantation, are trapped into a dislocation loop layer.
Method used
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Embodiment Construction
[0029] Hereinafter, an MIS transistor structure according to an embodiment of the present invention will be described with reference to FIG. 1(a).
[0030] As shown in FIG. 1(a), a poly-metal or polysilicon gate electrode 12 is formed over a semiconductor substrate 10 of p-type silicon with a gate insulating film 11 of a silicon dioxide or silicon oxynitride film interposed therebetween. A p-type dopant diffused layer 13 to be a channel region is formed under the gate electrode 12 in a surface region of the semiconductor substrate 10 through diffusion of indium, for example.
[0031] In respective regions on both sides of the p-type dopant diffused layer 13 (i.e., regions to be source / drain regions), high-concentration dopant diffused layer 14, n-type extended high-concentration dopant diffused layer 15 and pocket dopant diffused layer 16 have been formed. The high-concentration dopant diffused layer 14 is formed to have a deep junction by diffusing an n-type dopant (e.g., arsenic) ther...
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A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.
Description
BACKGROUND OF THE INVENTION [0001] The present invention relates to a semiconductor device, which has a superfine structure contributing to ultralarge-scale integration of a semiconductor integrated circuit and can operate at a high speed with its power dissipation reduced, and also relates to a method for fabricating the same. [0002] As ultralarge-scale integration of semiconductor integrated circuits advances, miniaturization of MIS transistors is demanded more and more strongly. For that purpose, an MIS transistor with a shallow junction is now in high demand. [0003]FIG. 5 illustrates a cross-sectional structure for a known MIS transistor with a shallow junction. A gate electrode 3 has been formed over a p-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. In respective surface regions of the semiconductor substrate 1 that are located on both sides of the gate electrode 3 (i.e., regions to be source / drain regions), high-concentration dopant diff...
Claims
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IPC IPC(8): H01L29/76
CPCH01L21/26513H01L29/6659H01L29/7833
InventorNODA, TAIJIUMIMOTO, HIROYUKIODANAKA, SHINJI
OwnerPANASONIC CORP