Methods and apparatus for adaptively adjusting a data receiver

Abstract

Offsets and timing skews in data signals captured in a data receiver are reduced by adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. The data receiver may incorporate a trip point adjustor that receives the set of adjustment vectors from the data corrector to adjust its trip point.

Description

RELATED APPLICATIONS [0001] This application is a Divisional of U.S. application Ser. No. 10 / 075,189, filed Feb. 13, 2002, which is incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION [0002] This invention relates generally to integrated circuit devices such as a memory device. More particularly, the present invention relates to a system and process for adjusting parameters of data receivers used in integrated circuit devices. BACKGROUND OF THE INVENTION [0003] Integrated circuit devices have long been the building blocks for a wide variety of applications. One of the largest applications for integrated circuits has been in the field of digital computers, where the development of smaller feature sizes for the integrated circuit has allowed for greater capacity and flexibility in operating a digital computer. In particular, the developments in integrated circuits have provided for increased memory capacity and different types of memory devices. One such memory device is...

AI Technical Summary

Problems solved by technology

However, DDR and similar memory devices utilize non-differential signaling for data signals input on the device data pins.

As a result, the received data signals exhibit timing skew relative to the received clock signals, when the signaling levels depart from ideal.

The non-differential signals and their sensitivity to the system voltage reference, VREF, may result in data signal offsets, which requires some compromise in building the receivers used in applications such as memory devices.

As a result of these design compromises, the internal signals after capture generally do not have the same duty cycle integrity as the system clock signal.

Invariably, the p to n drive strength ratios are not as balanced as initially designed.

As a result, imbalances in a duty cycle may occur, or the rise and fall times of the data signal and that of a data buffer may not be matched as desired.

As a result, some timing skews relative to the received clock signal may occur.

Then, generally, as data is sent from the data receivers to data latches, any kind of timing skew incurred in the data receivers translates into set-up and hold timing problems.

Further, any noise on the VREF input to the receiver could potentially affect the timing of the output signal in a high speed device.

Typically, once the integrated circuit has been made, data signal offsets and timing skews are not corrected during operation of the processed integrated circuit.

Such an approach will not fully address the problems previously discussed.

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