System and method for light weight task switching when a shared memory condition is signaled
a task switching and shared memory technology, applied in the field of system and method for lightweight task switching when a, can solve the problems of system performance decline and task switching typically occurring at pre-set levels
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[0029] The following is intended to provide a detailed description of an example of the invention and should not be taken to be limiting of the invention itself. Rather, any number of variations may fall within the scope of the invention, which is defined in the claims following the description.
[0030]FIG. 1 is a diagram of a processor switching tasks based upon acquiring a mutex lock. Synergistic processing complex (SPC) 100 includes synergistic processing unit (SPU) 110, which processes thread A 120 (e.g., a first thread). SPU 110 is preferably a single instruction, multiple data (SIMD) processor, such as a digital signal processor, a microcontroller, a microprocessor, or a combination of these cores. During execution, thread A 120 requests external data that is located in cache 150. For example, thread A 120 may wish to update a linked data structure that is located in cache 150. SPU 110 issues get lock line reservation 160 to L2 140 corresponding to thread A 120's request. Get l...
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