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Thermal stratification test apparatus and method providing cyclical and steady-state stratified environments

a technology of thermal stratification and test apparatus, which is applied in the direction of lighting and heating apparatus, individual semiconductor device testing, instruments, etc., can solve the problems of substantial capital cost to chip and pba manufacturer, and design flaws will not be discovered

Inactive Publication Date: 2007-06-14
INTEL CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Even so, some design flaws will not be discovered.
Undiscovered design errors can result in a substantial capital cost to the chip and PBA manufacturer.

Method used

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  • Thermal stratification test apparatus and method providing cyclical and steady-state stratified environments
  • Thermal stratification test apparatus and method providing cyclical and steady-state stratified environments
  • Thermal stratification test apparatus and method providing cyclical and steady-state stratified environments

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Embodiment Construction

[0028] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0029] The leading digit(s) of reference numbers appearing in the Figures generally corresponds to the Figure number in which that component is first introduced, such that the same reference number is used throughout to refer to an identical component which appears in multiple Figures. The same reference number or label may refer to signals and connections, and the actual meaning will be clear from its use in the context of the description.

[0030] TERMINOLOGY

[0031] The terms chip, die, integrated circuit, monolithic device, semiconductor device, and microelectronic device, are used in...

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Abstract

A method and apparatus for a thermal stratification test providing cyclical and steady-state stratified environments. In order to test an electronic device, for example one having one or more levels of ball-grid-array interconnections, e.g., connecting a chip to a flip-chip substrate and connecting the flip-chip substrate to a printed circuit board of a device, an apparatus and method are provided to heat one side of the device while cooling the second side. In some embodiments, the process is then reversed to cool the first side and heat the second. Some embodiments repeat the cycle of heat-cool-heat-cool several times, and then perform functional tests of the electronic circuitry. In some embodiments, the functional tests are performed in one or more thermal-stratification configurations after cycling at more extreme thermal stratification setups. In some embodiments, a test that emphasizes solder creep is employed.

Description

RELATED APPLICATIONS [0001] This application is a Divisional of U.S. application Ser. No. 10 / 389,632 filed Mar. 13, 2003, which is incorporated herein by reference.FIELD OF THE INVENTION [0002] This invention relates to the field of electronic circuit testing devices and methods, and more specifically to a method and apparatus for testing circuits in cyclical and steady-state thermally stratified environments. BACKGROUND OF THE INVENTION [0003] Packaged electronic chips that are mounted on printed circuit boards (PCBs) typically need to be tested. Frequently, prior testing was done at a wafer level after the chips have been largely fabricated, but before the chips are diced apart and packaged. Such a test is often called a wafer test and sort operation, since good chips can be sorted from bad chips that fail the test, saving time and money since the bad chips are discarded (or re-worked) before the effort of packaging the chips. Additional functional testing is often done after the ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G01R31/26G01R31/28
CPCG01R31/2817G01R31/2874G01R31/2862
Inventor FENK, C. WALTER
Owner INTEL CORP
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