Method and apparatus for parsing data streams

Abstract

A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

Description

REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. patent Application Ser. No. 10 / 238,805, filed on Sep. 11, 2002, which claims priority of U.S. Provisional Patent Application Ser. No. 60 / 364,052, filed on Mar. 15, 2002. The subject matter of the earlier filed applications is hereby incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to a system and method for generating a key to filter and mask non-compliant input combinations to render compliant output combinations. [0004] 2. Description of the Related Art [0005] In recent years, the unprecedented demands for faster operating electronic devices have placed a greater demand on the operating components of current electronic devices, which may operate at a lower rate. Some of these slower devices may need to interface with these faster state-of-the-art electronic devices. As a result of the speed mismatch between the logic designs of the ...

AI Technical Summary

Benefits of technology

This solution enables synchronized operation between devices with mismatched speeds, reducing the number of computations needed and simplifying the design of the data alignment circuit by filtering out illegal input combinations, thus enhancing interoperability and processing efficiency.

Problems solved by technology

Some of these slower devices may need to interface with these faster state-of-the-art electronic devices.

As a result of the speed mismatch between the logic designs of the faster devices and the slower devices, a timing difference between the interfaces of two such electronic devices may develop.

This timing difference may render the compatibility and exchange of data between two such devices more difficult to achieve.

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