Unlock instant, AI-driven research and patent intelligence for your innovation.

Components, methods and assemblies for multi-chip packages

a multi-chip module and assembly technology, applied in the direction of printed circuit manufacturing, printed circuit aspects, semiconductor/solid-state device details, etc., can solve the problems of increasing the consuming additional space for circuit panels and main circuit boards, and difficult to repair, let alone test, and improving the test and repair capabilities of multi-chip modules. , the effect of low overall height of the mcm

Inactive Publication Date: 2007-07-19
TESSERA INC
View PDF48 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009] One aspect of the invention provides a separate circuit module, or multi-chip module (MCM), wherein packaged semiconductor chips are attached to both sides of an interposer using connections in accordance with a land grid array (LGA) connection. Most preferably, no underfill material is used in the joints between the packaged semiconductor chips and the interposer to provide low overall height for the MCM. It is another object of the invention to improve the test and repair capabilities of the multi-chip module.

Problems solved by technology

This materially increases the cost of the circuit board.
However, the additional circuit panel and the additional layer of interconnections between this circuit panel and the main circuit board consume additional space.
Unfortunately, these types of packages are difficult to repair, let alone test, after assembly.
This increases the costs associated with producing, handling and stocking the various packages.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Components, methods and assemblies for multi-chip packages
  • Components, methods and assemblies for multi-chip packages
  • Components, methods and assemblies for multi-chip packages

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] A packaged semiconductor chip 100 is illustrated in FIG. 1. As used in this disclosure, the term “packaged semiconductor chip” refers to a unit including both the actual semiconductor element or “bare die” itself, and one or more components or layers which cover at least one surface or edge of the bare die. Typically, but not necessarily, a packaged chip has electrical connection elements distinct from the contacts of the bare die itself. As used in this disclosure, the term “standard packaged chip” refers to a packaged chip having electrical connection elements (whether or not distinct from the contacts of the bare die) disposed in a pattern conforming to an official or unofficial standard applicable to packaged chips. Most preferably, the standard packaged chips conform to a standard applicable to packaged chips intended for mounting to circuit boards. Illustratively, packaged semiconductor chip 100 is a Tessera® Compliant Chip as known in the art. However, other forms of p...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional application of U.S. patent application Ser. No. 10 / 683,097 filed on Oct. 10, 2003, entitled “Components, Methods and Assemblies For Multi-Chip Packages”, which claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 418,241, filed Oct. 11, 2002, the disclosures of which are hereby incorporated by reference herein.[0002] The U.S. government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract No. MD-A-904-02-C-1351 awarded by the National Security Agency.BACKGROUND OF THE INVENTION [0003] The present invention relates to microelectronic assemblies and to components and methods used for making the same. [0004] Microelectronic elements such as semiconductor chips ordinarily are mounted on circuit panels such as circuit boards. For example, a packaged semiconductor...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/00H01L25/10H05K1/14H05K3/34
CPCH01L25/105H01L2924/01078H01L2924/01327H01L2924/01079H01L2924/15311H01L2924/1532H01L2924/15331H01L2924/3511H05K1/141H05K3/3436H05K2201/10719H05K2203/1572H01L2924/01322H01L2224/16225H01L2225/1023H01L2225/1058H01L2225/107H01L2225/1005H01L2924/00H01L2224/05573H01L2224/05568H01L2224/05644H01L2924/00014H01L2224/05647H01L23/48H01L29/40
Inventor KIM, YOUNG-GONGIBSON, DAVIDWARNER, MICHAELDAMBERG, PHILIPOSBORN, PHILIP R.
Owner TESSERA INC